*****************************************************************************
*****************************************************************************
**                                                                         **
********** IEEE Components, Packaging, and Manufacturing Technology *********
**                                                                         **
*****************************************************************************
**        PACKAGING AND INTERCONNECTION ELECTRONIC NEWSLETTER              **
**                              (FULL)                                     **
**                         Volume 1, Number 4                              **
**                         October 25, 1994                                **
**                                                                         **
*****************************************************************************
*****************************************************************************


The Packaging and Interconnections Electronic Newsletter has
been established as a vehicle for rapid and broad dissemination
of information in the general area of interconnections and 
packaging (both electrical and optical) for both electronic
and optical systems.  The newsletter is sponsored by the IEEE
Components, Packaging, and Manufacturing Technology Society
(IEEE CPMT).  The University Relations Committee of the MCM Division
of the Electronic Industries Assoication (EIA) is an affiliate of the
newsletter.

The editor of this newsletter is
        Stuart K. Tewksbury
        Microelectronic Systems Research Center
        Dept. Electrical and Computer Engineering
        Eng. Science Bldg. 827
        West Virginia University
        Morgantown, WV 26506
        Tel: (304)293-6371  ext 512
        Fax: (304)293-7486
        Email: s.tewksbury@ieee.org

Full copies as well as summaries and tables of contents of this and earlier
newsletters are available by ftp or gopher to msrc.wvu.edu (157.182.197.50).


        
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
<<<<<<<<<<<>>>>>>>>>>>>>>>>>>
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
    
To subscribe to the PKG_NEWS, send an e-mail
message to "pkg_news@msrc.wvu.edu".  The body of the message should
include the following:
    i)  Full name
   ii)  Full mailing address
  iii)  Telephone number
   iv)  Fax number
    v)  E-Mail address
   vi)  One of the following options.
        a) "OPTION TOC"  (for table of contents only)
        b) "OPTION TOC+SUM" (for table of contents and summary)
        c) "OPTION FULL"  (for full copy of newsletter)

***SUBMISSION OF MATERIAL FOR PKG_NEWS***

    Send information to be included in the PKG_NEWS by e-mail to
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   will not reformat submitted information but will advise sender
   of any problems.


*****************************************************************************
**************************  IEEE CPMT ENEWS  ********************************
*******************        Table of Contents        *************************
*****************************************************************************
*****************************************************************************
 
1: RESOURCES:  None this issue


2: CALENDAR OF CONFERENCES/MEETINGS

   2.1  1995 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM: CALL FOR PAPERS
           (April 3-6, 1995, Las Vegas, Nevada)
           (Submission Deadline: Sept. 23, 1994 
   
           
3  TC-6 NEWS (IEEE CPMT: June 2, 1994: CPMT Newsletter).

   3.1  Automotive Electronic Packaging: 
           
4: TRADE JOURNAL NEWS/ARTICLES

   4.1  NEWS: "Diamond-copper-silver alloy developed for MCM substrates"  
           (July, 1994, Solid State Technology, p 36).         


5: BOOKS

   5.1  "Handbook of Electronics Packaging Design and Engineering," 
           second edition by Bernard S. Matisoff. 1990. Van Nostrand Reinhold

           
           
           
*****************************************************************************
**************************  IEEE CPMT ENEWS  ********************************
**************************     SECTION 2     ********************************
*************                                                  **************
*************     SCHEDULE OF CONFERENCES/MEETINGS             **************
*************                                                  **************
*****************************************************************************
*****************************************************************************


----------------------------------------------------------------------------
*ITEM 2.1   Listing of ISHM 94 conferences and workshops.  For more information,
            ISHM at (800)535-ISHM or (703)758-1060.
----------------------------------------------------------------------------
                
        Oct 31-Nov 2:  Flat Panel Packaging Workshop, Fla Keys
        Nov. 11:       MCM '95 Call for papers deadline
        Nov. 15-17:    ISHM '94
        Dec. 12-14:    MMRC Winter Workshop, Torrey Pines, CA

----------------------------------------------------------------------------
*ITEM 2.2   Another listing of packaging conferences/workshops
            (Electronic Packaging and Production, Aug 94)
----------------------------------------------------------------------------
                
        Nov. 8-12:   Electronica
                     Munich, Germany
                     Contact: Kallman Associates, (201)652-7070.

        Nov. 14-18:  Comdex Fall Show
                     Las Vegas, Nev.
                     Contact: Interface Group, (617)449-6600.

        Nov. 15-17:  ISHM Symposium
                     Boston, MA
                     Contact:  ISHM, (703)758-1060.

        Dec. 5-9:    Pronic '94
                     Paris, France
                     Contact: Blenheim Group, (617)426-8200.

        Dec. 7-9:    TMRC/AMRC Meeting
                     San Diego, CA
                     Contact:  IPC, (708)677-2850.

        Jan. 18-19:  San Diego Electronics Show
                     San Diego, CA
                     Contact: Epic Enterprises, (619)294-2999.

        Feb. 26 - March 2:  NEPCON West '95
                     Anaheim, CA
                     Contact: Reed Exhibition Companies, (203)964-0000.

       April 19-21:  Int. Conf. on MCMs
                     Denver, CO
                     Contact: ISHM, (703)471-0066 

        

----------------------------------------------------------------------------
*ITEM 2.3   3rd Topical Meeting on Electrical Performance of Electronics
            Packaging.  Nov. 2-4, 1994.  Monterey, CA.  Sponsored by
            IEEE Microwave Theory and Techniques Society and IEEE Components
            Packaging and Manufacturing Technology Society.
----------------------------------------------------------------------------

   "This is the third meeting in this topical series.  The general topic of
   the meeting is the electrical design, analysis, and characterization of
   electronic interconnections and packaging for performance-driven,
   high-speed/high complexity electronic systems.  A forum will be provided for
   the discussion of the following topics as they relate to chip-to-chip
   and on-chip interconnections in electronic systems.

          * Package analysis, including numerical methods and algorithms;
            electro-magnetic analysis tools; advances in transmission-line
            techniques.

          * New and innovative interconnect and packaging structures and their
            electrical performance.

          * RF/microwave packaging structures and their electrical performance.

          * MMIC modules and high density packaging.

          * Experimental characterization techniques and testing procedures.

          * EMC/EMI effects; prediction and measurement of radiation
            from interconnect structures and packaged systems.

          * Electrical requirements, limits of performance.

          * Novel designs, design methods, wire placement and routing systems.

          * Low cost, high volume packaging

          * Optoelectronic packaging; structure and system applications.

   For further information, contact 
          V.K. Tripathi, Tel: (503)737-2988    Fax: (503)737-1300
                         email: vkt@ece.orst.edu

     OR

         A. Cangellaris, Tel: (602)621-4521    Fax: (602)621-2999
                        email: cangellaris@ece.arizona.edu



----------------------------------------------------------------------------
*ITEM 2.4   CALL FOR PAPERS 

             Seventeenth (1995) IEEE/CPMT INTERNATIONAL 
             ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM
            October 2-4, 1995 - Hyatt Hotel - Austin, TX USA

            "Manufacturing Technologies--Present and Future"
----------------------------------------------------------------------------


   The International Electronics Manufacturing Technology (IEMT) Symposium is
an international forum for the presentation of research, development, and
application of technologies and systems for use in the manufacture of
electronic components, assemblies, and systems.  

   The audience for the IEMT Symposium includes engineers, scientists,
managers and others involved in the development, improvement, and application
of electronics manufacturing technologies.  It will feature technical
sessions on the most critical challenges facing electronics manufacturers
into the twenty-first century.  Each session will include  papers on current
leading-edge work in the area and an opportunity for dialogue with the
experts.  The Symposium is now soliciting technical papers on current work in
areas listed below.

   The IEMT Symposia normally are held twice each year:  each autumn in the
United States and each spring alternating between Europe and Japan.


Integrating Design and Manufacturing
   -Agile Manufacturing
   -Applied Concurrent Engineering & Cycle Time Reduction
   -Design for Manufacturability, Profit, the Environment, etc.
   -Concurrent Engineering CAD/CAM Tools & Frameworks
   -Intelligent Manufacturing (AI, Neural Nets, Closed Loop Control)

Reducing Manufacturing Cost and Cycle Time
   -Low Cost, High Volume Manufacturing
   -Use of Multimedia (3D Imaging, Interface Design, Virtual Reality)
   -Self-Test and Burn-In
   -Improving and Reducing the Requirement for Inspection
   -Improving Quality and Process Control

Advanced Interconnect Developments
   -Displays, Computers, Telecommunications, Handheld Products
   -Multichip Modules and 3D Packaging
   -Fine Pitch Interconnect Improvements and Alternatives
   -Applied Photonics and Electro-Optics
   -Advanced Packaging (BGAs, flexible packaging, COB, COG)

Manufacturing Operations Improvement
   -CFC Elimination, Pb-free Soldering
   -Equipment Engineering, Automation, CIM
   -JIT System Development and Implementation
   -Shop Floor Scheduling and Operation
   -Optimizing Semiconductor Manufacturing

Manufacturing Analysis
   -Statistical Methods in Manufacturing
   -Joint Reliability & Mechanical Properties Measurement
   -Manufacturing Management Practices and Science
   -Placement Sequence Optimization
   -Manufacturing Tool, Equipment, Process Modeling, and Reliability

General Chairman:  
   Walt Trybula                       Phone: 512-356-3306
   SEMATECH                           FAX:   512-356-3525
   2706 Montopolis Dr.                Email: walt.trybula@sematech.org
   Austin, TX 78741 USA

Program Chairman
   Dr. Don Millard                    Phone: 518-276-6724
   Rensselaer Polytechnic Inst.       FAX:   518-276-2990
   110 8th St.                        Email: don_millard@dmi.rpi.edu
   Troy, NY 12180  USA        

Japan Liaison
   Dr. Takaaki Ohsaki                 Phone: 81-422-59-2511
   NTT Interdisciplinary Res. Labs    FAX:   81-422-59-2164
   9-11, Midori-cho 3-chome           Email: mika@aela.ntt.jp
   Musashino-shi, Tokyo, 180 JAPAN   

Taiwan Liaison
   Dr. Li-Chung Lee                   Phone: 886-35-916800
   ITRI, Matl's Research Lab          FAX:   886-35-820247
   Bldg. 77, 195 Chung Hsing Rd., Sec. 4
   Chutung, Hainchu, Taiwan 31015   

Europe Liaison
   Michel Salagoity                   Phone: 33-56-757470
   Solectron France                   FAX:   33-56-898136
   BP 6
   33611 Cestas, Cedex, FRANCE

Further Conference Information
   Peter Walsh                        Phone: 202-457-4932
   Electronic Industries Association  FAX:   202-457-4985
   2001 Pennsylvania Ave., NW
   Washington, DC  20006-1813  USA

Past Conference Publications
   Paul Wesling                       Phone: 408-285-9555
   Tandem Computers                   FAX:   408-285-9670
   10400 Ridgeview Court, LOC 208-57  Email: p.wesling@ieee.org
   Cupertino, CA  95014  USA


                    ABSTRACT SUBMISSION INSTRUCTIONS

      ! ! ! ! !  Deadline for Receipt:  March 17, 1995  ! ! ! ! !

           Please include the following:
              Name(Dr/Mr/Ms)         Company/Institution
              Paper Title            Address
              Author and co-authors  Phone, FAX, E-Mail

Mail, FAX, or Email to:
   Terry Chappell, Publications       Voice & FAX: 408-662-1936
   730 Encino Drive                   Alternate FAX: 408-688-5602
   Aptos, CA  95003  USA              Email:  tnchappell@aol.com

              ! ! ! ! !  Please note:  ! ! ! ! !  

        Most IEMT correspondance is conducted electronically.  
        Make sure to send your correct FAX and/or email numbers.

   To submit a paper, send an abstract of at least 250 words by March 17,
1995.  It must clearly describes the nature, scope, content, organization,
key points and significance of the proposed paper.  The paper must consist of
work or results not published previously. 

   Submission of an abstract represents a commitment to submit a cleared
manuscript by June 30, 1995.  It also represents a commitment to either
attend the conference or send a knowledgeable substitute who can answer
questions regarding the reported work.  It is the author's responsibility to
obtain internal company approvals consistent with these deadlines. 
 
   Authors will be notified of paper acceptance, with full instructions for
publication by April 24, 1995.  Camera-ready manuscripts are expected to be
from three to eight pages including diagrams, figures, and photographs.  As a
convenience, authors may pay a fee to have our subcontractor format the text
and figures.  Authors need only submit text on diskette or email together
with photos and figures.  Chappell Enterprises charges $25 plus $6 per figure
to do the formating.

   Copies of your paper may be shown to members of the technical press for
pre-conference publicity.  They may chose to quote up to 50 words from your
paper and publish your figures and diagrams.  If this would create a problem
for your company, please tell us when you submit an abstract. 

   The language for the Symposium and its publications is English.  The IEMT
Symposium is sponsored by the IEEE; however, IEEE membership is not required
to present a paper or to attend the Symposium.  Copies of past proceedings
are available for purchase.  Papers published in the Proceedings are eligible
for publication in the IEEE CPMT Transactions after normal review procedures.

----------------------------------------------------------------------------
*ITEM 2.5   1995 IEEE Semiconductor Thermal Measurement and Management
          (SEMI-THERM) Symposium (February 7-9, 1995, San Jose, CA  USA)
----------------------------------------------------------------------------


SEMI-THERM is an international forum for new developments in the
thermal characterization of electronic components and systems.  With
a single track for its technical presentations, it fosters interchange
between academic and industrial communities on advances in the thermal
management of electronic systems.  There are also technical workshops,
tutorials, vendor exhibits, and optional short courses.  Primary themes:
    -- Thermal Characterization
    -- Analytical and Computational Thermal Modeling
    -- Measurement Techniques, including Temperature, Fluid Flow,
             and Thermal-Mechanical Properties
    -- Thermal Reliability Screening and Testing
The Symposium is at the Red Lion Hotel, San Jose, California, in the
heart of Silicon Valley.

The Advance Program for the 11th SEMI-THERM is now available; call
Bonnie Crystall or Walt Schuch at 1+602-345-1118, or FAX your request
to 1+602-345-1119.  For information about past Conference Proceedings,
contact Paul Wesling at p.wesling@ieee.org.

General Chair: David Blackburn, NIST     (blackburn@sed.eeel.nist.gov)
Program Chair: Prof. Vincent Manno, Tufts Univ (vmanno@pearl.tufts.edu)



----------------------------------------------------------------------------
*ITEM 2.6   ISHM Flat Panel Display Packaging  Advanced Technology Workshop
                   Cheeca Lodge, Islamorada, Florida
                   October 31 - November 2
                       Organizer: Jack Balde, IDC
                       Program Chairs: Ron Pacheco, Digital Equipment Corp. &
                                       Dave Palmer, Sandia National Labs
----------------------------------------------------------------------------
   ADVANCE PROGRAM

First day October 31, 1994:

  Noon  Keynote Addresses

      1. "Future DoD Flat Panel Display Directions; Impact on
         Packaging", Mark  Hartney; ARPA
      2. "The Trends in LCD Driver Packaging", Jackson Hwang, MCC
         Internation Liaison Office

  Afternoon Session  Display Connectors and Cables (Chair: Larry Kopp, AMP)
      1. "Economical Options for Display Connections," Pat Maher,
          Hiroshi
      2.  "Connectors for Flat Panel Displays", David Shaff, JAE
      3. "Flat Panel Interconnection Technology", Bert Sharp, AMP

  Evening Session  "Conductive Adhesive Interconnect"
         Chairs: Joel Gerber, 3M and John Emerson, Sandia National Labs
     1. "Three Dimensional Printing", Printon, Inc., Donald Wunsch
     2. "Chip-on-Glass for Portable Products", Stefan Peana,
         Motorola
     3. "Options for Adhesively Bonded Display Driver Interconnect",
         William Ballard 3M
     4. "Advanced Conductive Adhesives Interconnects" National Center
         for  Manufacturing Science, Speaker TBA

 Second Day, November 1

  Morning Session  Display Packaging Requirements Session
     Chairs: Bill Turner, Xerox Parc, and Jim Jorgensen, Sandia Labs

     1. "Overview of Flat Panel Display Industry Packaging;
         Requirements  and Issues"  Bill Turner; Xerox PARC
     2. "Flat Panel Display Driver Chips, Requirements and Issues",
         Alex Earhart, Vivid Semiconductor
     3. "Overview of Electronic Interconnect for EL Displays", Dave
         Watson/Pradip Patel; Planar Systems, Inc.

     4. "TAB Design for FPD Driver Chips"  Vivek Dutta; Cirrus Logic
     5. "TAB Bonding on Flat Panel Displays"  Gregory Lin; Xerox PARC
     6. "Laser Applications for FPDs"  Edward Swenson; Electro
         Scientific Industries, Inc.
     7. "A review of Electrical Interconnects for Emissive Vacuum
         Displays", James Cathey, Micron Display Technology

  Afternoon for free discussion and individual activities

  Evening Session  "Encapsulation and Corrosion Protection"
        Chairs: Kurt Gsteiger, Florida Institute of Technology and C. P.
            Wong,  AT&T Bell Labs

     1. "Environmental Factors Influencing LCD Designs", Bob Rhoades,
         Standish Industries
     2. "Non-Hermetic Protection of IC's: Some Recent Results", Ralph
         J.  Jaccodine, Lehigh University
     3. "Reliability Review of Thin Plastic Packages", Mark Fujimori,
         Nitto  Denko America Inc.
     4. "Robust Protection of Bare Die", Robert C. Camilletti, Dow
         Corning  Corporation

 Third Day: November 2
    Morning Session "Metallurgical Interconnect"
         Chairs: Bert Haskell, MCC/Kodak and Steve Gallo, DuPont

     1. "Analysis of display chip in SONY structure," Dan Barton,
         Sandia  National Labs
     2. "The Technology Considerations for InSnO Conductors", Bert
         Haskell,  MCC
     3. "Hot Bar Chip Bonding", Tom Todd, Toddco General, Inc.
     4. "Soldering or Conductive Adhesive for Displays?", Ken Gilleo
         (tentative), Alpha Metals
     5. "Compliant Bumps:the Alternative Connection to ITO
         Conductors",  Phil Spletter, MCC
     6. "Conductive adhesive for flip chip on glass", TBA, Ablestick



 Registration Information:

   ISHM member:    $325
   Non-member:     $390 (includes 1 year membership in ISHM)
   Speaker/Chair:  $185
   Spouse/Guest:   $150 (workshop meals)

   The registration fees will cover the workshop meals and a bound
   copy of the abstracts.

    Fees should be forwarded to:

          ISHM, 1850 Centennial Park Dr. Suite 105, Reston, VA 22091
          ISHM can also be contacted at 800-535-ISHM

    The workshop will be held in the Cheeca Lodge in the island
    Islamorada, which is 75 miles south of Miami on Highway 1, Mile
    marker 82. Accommodations are to be made directly with the hotel
    800-327-2888 (or fax 305-664-2865). The rooms are $145/nite,
    single or double occupancy. Room reservations should be made by
    October 7.



       
----------------------------------------------------------------------------
*ITEM 2.7  ANNOUNCEMENT:  IEEE/LEOS 1995 SUMMER TOPICAL MEETINGS
                 August 7-11, 1995
                  KEYSTONE RESORT
                 Keystone, Colorado
    ABSTRACT & SUMMARY DEADLINE MARCH 3, 1995

    SEPARATE MEETINGS ARE SUMMARIZED BELOW
----------------------------------------------------------------------------


(A) TECHNOLOGIES FOR A GLOBAL INFORMATION INFRASTRUCTURE
               August 7-9, 1995

   Organizers:
      Ivan P. Kaminow, AT&T Bell Labs, Holmdel, NJ
      Richard E. Wagner, Bellcore, Red Bank, NJ
      Alan E. Willner, USC, Los Angeles, CA

   Scope:
      This topical meeting provides a forum for exploring the
      technologies that may be needed to implement broadband
      global access to interactive multimedia services.  The
      technologies include traditional optical communications and
      network management desciplines plus the means to bring
      interactive voice, data and video to residences and businesses
      at affordable costs.  The meeting is intended to cover global
      and regional transport networks and local access network
      technologies at digital rates ranging from Gb/s for transport to
      Mb/s for access.  The meeting foprmat will include invited and
      contributed talk on the more familiar optical topics, as well as
      tutorial and contribute talks on topics that usually fall outside
      the scope of lightwave techniques but are key to braodband
      global access.

   We solicit papers on the following topics:

      * Analog and Digital Transport
      * Rearrangeable and Transparent Optical Networks
      * Network Architectures
      * Fiber/Coax Networks
      * WDM Components and Networks
      * Network Management and Control
      * Testbed Demonstrations
      * Business and Economic Studies
      * Government's Role in Optical Networking

   Tutorial talks and solicited contributed papers will also cover
   the following related disciplines:

      * Multimedia Technologies
      * ATM and Other Electronic Access Techniques
      * LAN/MAN/WAN Networks
      * Video Server Technology
      * Business Considerations
      * Image Applications Over Internet
      * Consumer Electronics (e.g., Set-top Boxes)


(B) FLAT PANEL DISPLAY TECHNOLOGY
      August 7-9, 1995

   Organizer:
      Stephen Forrest, Princeton University, Princeton, NJ

   Scope:
      This conference will focus on recent advances in flat panel
      display materials, devices, and architectural technology. 
      Original papers are being solicited in all areas relating to the
      latest advances of novel, flat panel display technology. 
      Particular focus is on advances in light emitting materials such
      as the wide gap III-V and II-VI semiconducts, liquid crystals,
      vacuum deposited organics and polymers.  Novel approaches
      to backplane, active matrix thin film transistor technology will
      also be covered.  In addition, papers discussing architectural
      concepts for creating, maintaining and manipulating image data
      in the context of "intelligent displays" will be encouraged.



(C) RF OPTOELECTRONICS
      August 9-11, 1995

   Organizers:
      Charles Cox, MIT Lincoln Lab, Lexington, MA
      Ming Wu, UCLA, Los Angeles, CA
      Chi Lee, University of Maryland, College Park, MD
      Peter Herczfeld, Drexel University, Philadelphia, PA

   Scope:
      This meeting is concerned with devices and links required to
      convey microwave and millimeter wave signals over optical
      fibrs.  Applications for this work include the rapidly emerging
      field of optically fed wireless communications as well as more
      established fields such as CATV distributions, optically
      controlled phased array antenna and antenna remoting.  The
      major impediment to the wider use of this technology is the
      cost and reliability of the components, particularly those that
      constitute the optical transmitters and receivers.  Of special
      interest will be those efforts which address the problems of
      cost and reliability, such as the large scale integration of
      photonic and microwave components on a single chip.  The
      objective of the Topical Meeting is to bring together the
      technical communities representing device development and
      fabrication,  link design, and system users to explore future
      directions of this field.



(D) ICs FOR NEW AGE LIGHTWAVE COMMUNICATIONS
      August 9-11, 1995

   Organizers:
      Tran V. Muoi, Optical Communications Products, Inc.
      Robert G. Swartz, AT&T, Holmdel, NJ

   Scope:
      Advanced integrated circuits have traditionally played a crucial
      role in the practical realizationa and commercialization of fiber
      optic communications systems.  In the 1980's, rapid advances
      in high speed IC technologies and design techniques marched
      hand in hand with corresponding advances on the optical side
      (fiber and devices) leading to a staggering rate of increase in
      optical capacity.  However, as the bandwidth capability of
      optical components increases beyond 10 Gbit/s, the electronics
      has become a bottleneck.  As a result, high speed IC
      technologies are developing rapidly from all angles:  Silicon-
      based and III-V compound-based processes, FET and HEMT,
      homojunction and heterojunction bipolar technology, novel
      circuit design concepts...

      Additionaly, at the same time that demand for traditional point-
      to-point capacity is surging, Fiber-in-the-Loop (FITL) and
      Fiber-to-the-Home (FTTH) have leaped on-stage with new
      demands on optical devices and special purpose ICs.  For
      example, the Passive Optical Network (PON) architecture puts
      stringent demand on the burst-mode operation of optical
      transmitters and receivers.

      The aim of the Summer Topical Meeting is to provide a forum
      where technical experts representing all aspects of IC design,
      IC circuit design and transmission equipment/system design can
      meet to share ideas and report progress.

   Topics of interest include:
       *   Competing Technologies:  Silicon (bipolar, CMOS,
           BiCMOS, SiGe HBT), and Compound Semiconductor
           (MESFET, HEMT & HBT based on GaAs & InP)
       *   Design Techniques and Demonstrtions of High Speed
           ICs (laser and LED drivers, preamplifiers
           AGC/limiting amplifiers, decision circuits, timing
           recovery, mux/demux, etc.)
       *   ICs for SONET/ATM systems and FDDI/HIPPI/Fiber
           Channel
       *   ICs for Passive Optical Networks
       *   Optoelectronic Integration and Optical Interconnects
       *   Electronics for Analog Optical Distribution (e.g.
           Fiber/Coax and Fiber/Microwave)
       *   Systems Results, Demonstrations and Implications for
           Optical Communications ICs
       *   Low Cost and High Performance Packaging of
           Electronic and Optoelectronic Components


SUBMISSION OF PAPERS

   All abstracts and original summaries must reach the LEOS
   Executive Office by March 3, 1995.  Send your paper to the
   following address:

      Summer Topicals 1995
      IEEE/LEOS
      445 Hoes Land, P.O. Box 1331
      Piscataway, NJ  08855-1331
      908-562-3897 (Phone)
      908-562-8434 (Facsimile)

PREPARATION OF ABSTRACT AND SUMMARY

   A limited number of original, unpublished contributed papers
   will be accepted for presentation.  Presentation times will be
   determined by the program committee.

   35-Word Abstract
      The abstract should be typed on a single sheet with the title at
      the top of the page, followed by the author's name, affiliation,
      complete return address and the text of the abstract.  If a paper
      has multiple authors from different organizations, each author's
      name and address should be listed separately after the title. 
      The abstract will appear in the advance program upon
      acceptance of the paper.

   The Summary
      The summary of up to two pages must be submitted in camera-
      ready form - typewritten, single spaced, on 8.5" x 11" white
      bond paper with 1" margins on all sides. The author must
      include equations, drawings, figures and references within this
      two-page limit.  Figures, tables and drawings must be camera-
      ready copy.  The first page must begin with the title of the
      paper followed by the author's name, affiliation and address. 
      The summary will be reproduced in the technical digest upon
      acceptance of the paper.

   For further information, or to be placed on the Call for Papers
      mailing list, please contact the IEEE/LEOS Executive Office
      at the above address or via phone (908-562-3893), facsimile
      (908-562-8434) or e-mail (e.b.cohen@ieee.org).

   Sponsored by the IEEE/Lasers and Electro-Optics Society and
   the Optical Society of America


----------------------------------------------------------------------------
*ITEM 2.8  ANNOUNCEMENT: 1995 WORKSHOP ON INTERCONNECTIONS WITHIN 
                         HIGH SPEED DIGITAL SYSTEMS

                            May 14-17, 1995
                          Picacho Plaza Hotel
                         Santa Fe, New Mexico


   Sponsored by the IEEE Lasers & Electro-Optics Society 
      and in cooperation with the IEEE Computer Society 
         and the IEEE Communications Society
----------------------------------------------------------------------------

   WORKSHOP SCOPE

      The IEEE Communications Society's Technical Committee on
      Interconnections within High-Speed Digital Systems will hold
      a Workshop on May 14-17, 1995, in Santa Fe, New Mexico.

      The rapid evolution of integrated circuit technology has led to
      dramatic improvements in the performance of advance
      computing and communications systems.  Future applications
      will require even more computational and communications
      power.  Even in today's systems, however, interconnections
      are often a bottleneck to achieving higher performance.  The
      purpose of this Workshop is to determine the interconnection
      requrements of emerging computer and communications
      systems and to evaluate advanced interconnection technologies
      in light of those requirements.  Because of the multidisciplinary
      nature of the problem, the Workshop brings together
      researchers and practitions with expertise in a variety of fields
      including electrical and optical interconnection technology,
      advanced system architectures, and the algorithms and
      appplications implemented in these systems.  The format of the
      Workshop is highly interactive.

   Workshop Chair
      Rick Lytel, Akzo Nobel Electronic Products Inc.

   Program Co-Chairs
      Rich Carson, Sandia National Laboratory
      Anis Husain, ARPA
      Ted Woodward, AT&T Bell Laboratories

   International Liaisons
      Martin Goodwin, GEC-Marconi, Caswell
      Arne Wallers, Ericsson Telecom AB
      Osamu Wada, Fujitsu Laboratories


   WORKSHOP OBJECTIVES

      To review the latest advances in electrical and optical
      interconnection technology at the component, packaging and
      subsystem level, and the implementation of these technologies
      in real systems

      To assess the impact of advances in computer and
      communications systems architechtures, algorithms and
      applications on requirements for high-speed interconnections

      To promote furture activity and interaction in matching
      interconnection technologies to the requrements of high-speed
      digital systems


   To receive information about contributing topics/papers for
   presentation, please contact:
      Rick Lytel
      Akzo Nobel Electronic Products Inc.
      250 C Twin Dolphin Drive 
      Redwood City, CA  94065
      Fax:  415-508-2959
      Email:  lytel@akzochip.com

   To be placed on the mailing list to receive further details about
   the Workshop, please contact:
      IEEE/LEOS
      445 Hoes Lane 
      P.O. Box 1331
      Piscataway, NJ  08855-1331
      Phone:  908-562-3894     Fax:  908-562-8434
      Email:  s.phillips@ieee.org



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**************************  IEEE CPMT ENEWS  ********************************
**************************     SECTION 3     ********************************
*************                                                  **************
*************               IEEE CPMT INFO                     **************
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----------------------------------------------------------------------------
*ITEM 3.1  CPMT Service for Unemployed Professional  
----------------------------------------------------------------------------
   As part of IEEE CPMT's ongoing effort to assist CPMT members who are
   unemplyed, or soon to be unemployed, IEEE CPMT is offering the opportunity
   to run a single-paragraph "Situation Wanted" ad in the CPMT Newsletter.
   This opportunity is intended for those seeking permanent positions (not for
   consultants or those looking for temporary assignments); graduating
   students intending to work in the fields covered by CPMT may use this
   service.

   The ads should be sent to
         Dr. David Palmer
         Sandia Laboratories
         M/S 1082, Org 1333
         PO Box 5800
         Albuquerque, NM 87185
         Fax: +1-505-844-2991
         email: dpalmer@ieee.org

   Your ad will be run in the next available CPMT Newsletter; on request
   it will be continued for an additional issue of the Newsletter.

   Below is a sample format for the ads.  Ads are strictly limited to a
   60-word maximum.  Names are optional in the ads; please include a
   telephone and/or FAX number where you can be reached by interested parties.

       -----------------------------------------------------
       SAMPLE  Matierials Engineer seeking packaging engineering position,
       FORMAT  BS-EE, MS-MatSci, 14 years experience in devlopment of both
               military and commercial hybrid and MCM packaging.  Extensive
               experience in thermal design and analysis, including CAD, and
               in package qualification and failure analysis.  Good verbal and
               written communication skils.  Prefer Calif. location.  Call
               408-xxx-xxx for resume.  (Sept. 94)
      -----------------------------------------------------
        

        
        
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**************************  IEEE CPMT ENEWS  ********************************
**************************     SECTION 4     ********************************
*************                                                  **************
*************        TRADE JOURNAL NEWS/ARTICLES               **************
*************                                                  **************
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*****************************************************************************
        
----------------------------------------------------------------------------
*ITEM 4.1  Ad-Hoc group addresses 3-D packaging standards.
           (Electronic Design:  Sept. 19, 1994)  
----------------------------------------------------------------------------
   An ad-hoc group, which developed out of informal meetings at the Spring
   Conf. on Solid State Memory Technologies, has been formed to develop practical
   standards for 3D packaging that would be acceptable to a wide range of
   product developers and suppliers of materials, process equipment, and ICs.
   "Some of the issues that the group plans to address include die sizes,
   known-good die (KGD), trace density, heat-transfer analysis and
   methodologies, radiation tolerance, topology, known-good stacks (KGS), 
   bonding processes, software tools for place-and-route, testability, 
   redundancy, error management, signal integrity, and repairability.
   Present members representatives from Controlex Corp., Datatape Inc.,
   General Electric Corp., Harris Corp., Honeywell, Loral Federal Systems,
   NASA/Jet Propulsion Labs, TRW Components International, Tanner Research,
   TechSearch International, and Texas Instruments."  

   For more information, contact Bruce Kaufman of Conrolex at
   (813)780-8877.

----------------------------------------------------------------------------
*ITEM 4.2  "Industry Trends: A Tour of Tomorrow"
           Donald Seraphin (Author and consultant)
           (Printed Circuit Fabrication:  Sept. 9, 1994, pp. 18-25)  
----------------------------------------------------------------------------

   "The ecoonomic environment amnd new product development trends in the
   electronics and PCB industry show a highly favorable continued growth.
   The promising areas for expansion include PCMCIA cares and MCM-Ls, which
   are needed to build compact, powerful personal systems for the consumer
   market.  Very high interconnection densities are nor required for the
   evolving computer and telecommunications technologies in order to support
   the array components being introduced for increasing packaging area
   efficiency.  Composite materials under development will play a significant
   role in processability and design for these and other applications of the
   late 1990s."  -- Introduction.

----------------------------------------------------------------------------
*ITEM 4.3  "Testing Known-Good Die:  Practical Solutions at Last!"
           H. Green and Fariborz Agahdel (MicroModule Systems) and
               T. Gucciardi (Texas Instruments)
           (Semiconductor International:  Sept. 1994, pp. 48-52)  
----------------------------------------------------------------------------

   "As electronic products continue to shrink in size and overall form
   factor, many designers are turning to multichip modules and chip-on-board
   technologies, which require the availability of known-good die (KGD).
   These are defined as bare, unpackaged semiconductor products with the
   reliability and quality of burned-in and tested packaged parts.  
   Implementing KGD test technology has been a multiyear effort throughout
   the semiconductor industry to develop processes for die handling, burn-in,
   and test."  -- At a Glance

----------------------------------------------------------------------------
*ITEM 4.4  "A Cool Package for the 90s"
           A.K. Knudsen and P.E. Garrou (Dow Chemical)
           (IEEE Circuits and Devices Magazine:  Sept. 1994, pp. 20-25)  
----------------------------------------------------------------------------

   "Dramatic increases in the power handling capacity of ever smaller
   electronic devices are placing a number of significant demands upon
   today's materials.  Chief among these is the need to dissipate heat
   efficiently.  Plastic packages, used in the vast majority of electronic
   devices, are inexpensive but have low thermal conductivity, typically
   less than 1W/mK.  Ceramic packaging, on the other hand, is significantly
   more expensive but offers a variety of properties that may be essential
   for the reliable operation of critical devices.  Aluminum nitride, a
   relatively new and intriguing ceramic, may ultimately provide the best
   solution for a wide variety of packaging tasks.  Indeed, AIN-based
   packages have reached the marketplace.  One obstacle remains, however:
   its relatively high cost."  -- Introduction.

----------------------------------------------------------------------------
*ITEM 4.5  "Future Rosy for 3-D Packaging, Report Predicts"
           R. Iscoff (magazine editor)
           (Semiconductor International:  Aug. 1994, p. 26)  
----------------------------------------------------------------------------

   New item discusses some general issues surrounding 3D packaging, 
   highlighting a report by Robert Crowley, vice president of TechSearch
   International.  For information on this 300 page report, contact
   TechSearch International at 
                 Tel:  (512)343-4508
                 Fax:  (512)343-4509

----------------------------------------------------------------------------
*ITEM 4.6  "Memory-Chip Stacks Send Density Skyward"
           David Maliniak
           (Electronic Design:  Aug 22, 1994, pp. 69-75)  
----------------------------------------------------------------------------

   Article discusses the 3D memory approach of Cubic Memory Inc (CMI).  Three
   approaches extending interconnections directly through the silicon die are
   described:  the "large-hole process", the "small hole process", and the "Vertical
   Interconnect Process".  Reports that CMI is offering two forms of memory
   modules for expansion of portable-system memory.  One is a 3D family of 88-pin
   JEDEC memory modules in capacities of 16, 32, 64, and 128 Mbytes.  Summary at
   end of article states that the 88-pin JEDEC module with 16 Mbyte of memory
   will be available in Sept. at a suggested price of $995.  32-, 64-, and
   128-Mbyte modules are expected in the last quarter, with pricing projected
   to be $1995, $3995, and $7995, respectively.

   For information, contact Cubic Memory Inc., 27 Janis Way, Scotts Valley,
   Ca 95066.  Phone:  (408)438-1887.  Fax:  (408)438-1890.

----------------------------------------------------------------------------
*ITEM 4.7  News Item
           "EDIF PCB Standard will Debut this Fall"
           (Electronic Design:  Sept. 5, 1994, p. 30)  
----------------------------------------------------------------------------

   "The Electronic Industries Association (EIA) will release the ELectronic
   Design Interchange Format (EDIF) for pc boards this November.  The EDIF PCB
   information model contains 155 entries that are catagorized into 14 sections,
   including material, geometry, package library, and footprint mapping....
   A key component of the EDIF PCB is the Design Rule feature, which helps 
   represent simple layout features, complex sub-layouts, pad stack usages,
   physical nets, sub-nets, layout text, power-plane template, and probe-point
   refrences.  Another key section, Assembly Board, will address component
   net-list definition, component placement, route and wire-bond
   assembled physical nets, association between components and their footprints,
   and function-allocation information.  EDIF PCB with multichip module constructs
   and complex design rules is due out at a later date and will represent an
   entirely new direction for the standard.  Copies of the specification and
   licensing agreement can be obtained from the EIA's Patti Rusher at
   (703)527-7002.

----------------------------------------------------------------------------
*ITEM 4.8  "Ball Grid Arrays Target High-Performance Needs"
           (Electronic Products:  Sept. 1994, p. 17)  
                            AND
           "Advanced Ball-Grid Array Addresses Cost and Size Issues"
           (Electronic Design:  Aug 8, 1994, p. 40-42)
----------------------------------------------------------------------------

   Brief article highlights SuperBGA technology introduced by Amkor
   Electronics, Inc. (Chandler, AZ).  Package is targeted for applications
   between the lower cost plastic BGAs and higher performance but costlier
   ceramic BGAs.  For information, contact Gil Olachea, Amkor Electronics,
   (602)821-5000.

----------------------------------------------------------------------------
*ITEM 4.9  "Testing MCMs with Boundary Scan"
           Tom Storey (Loral Federal Systems)
           (EE-Evaluation Engineering:  Sept. 1994, pp. 88-93)  
----------------------------------------------------------------------------

   Author provides an overview of boundary scan techniques for testing
   MCMs.  Tom Storey:  Loral Federal Systems, Manassas, VA.  (703)367-6924

----------------------------------------------------------------------------
*ITEM 4.10  "The How and Why of Multichip Module Testing"
           Ken Posse (Hewlett-Packagd Co.)
           (EE-Evaluation Engineering:  Sept. 1994, pp. 94-98)  
----------------------------------------------------------------------------

   Author provides an overview of boundary scan techniques for testing
   MCMs.  Ken Posse:  HP Co., Loveland, CO.  (303)679-5000

----------------------------------------------------------------------------
*ITEM 4.11  "Bare Die Test Strategies for the MCM Market"
           Marlene J. Begay (Motorola Semiconductor Products)
           (Solid State Technology:  June 1994, pp. 65-75)  
----------------------------------------------------------------------------

   "Growth of the MCM market has been slowed by high costs resulting from the
   low yields of untested chips or the cost pehaly of known good dice (KGD).
   This article examines the dilemma from the viewpoint of semiconductor
   producers, who are being forced to find ways around the techical barriers
   to cost-effective KGD chips that can match packaged chip standards.
   The required spectrum of test includes parametric, functional, full-speed,
   elevated temperature and accelerated burn-in procedures.  These test may
   be performed at either the bare-die or, preferably, the whole-wafer
   level."  -- Abstract.

----------------------------------------------------------------------------
*ITEM 4.12  "IC Packaging moves to the front of the design cycle"
           Mike Donlin (Magazine editor)
           (Computer Design:  July 1994, pp. 57-64)  
----------------------------------------------------------------------------

   Article is an overview of packaging, with a focus on BGA packaging.  Comments
   from various industry representatives regarding potentials and issues.

----------------------------------------------------------------------------
*ITEM 4.13  "Bare Die Economics Lesson"
           jack Tuck (Consultant)
           (Circuits Assembly:  Oct 1994, pp. 18-22)  
----------------------------------------------------------------------------

   Article gives general background discussion of costs associated with
   bare die testing.

----------------------------------------------------------------------------
*ITEM 4.14  "Understanding MCM Assembly and Testing"
           R. Bone, D. Elwell, R. McBride, W. Schenet, and
            M. Stelling (Hughes Microelectronics, Newport Beach, CA)
           (Solid State Technology:  October 1994, pp. 87-93)  
----------------------------------------------------------------------------

   "Multichip modules (MCMs) occupy the middle ground between
   integrated circuits and printed wiring boards (PWBs).  As such
   manufacturability and testability must be considered at each level
   of circuit and package design.  This article considers substrate and
   package selection and test strategies in the context of system
   reliability."  -- from abstract.
        
        
        
        
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**************************  IEEE CPMT ENEWS  ********************************
**************************     SECTION 5     ********************************
*************                                                  **************
*************                    BOOKS                         **************
*************                                                  **************
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*****************************************************************************

----------------------------------------------------------------------------        
*ITEM 5.1  "Materials in Microelectronic and Optoelectronic Packaging" 
            by H.C. Ling, K. Niwa, and V.N. Shukla.  
            American Ceramic Society, 471 pges, 1993.  ISBN 0-944904-63-7
----------------------------------------------------------------------------
   "Discover the next generation of packaging materials and fabrication
    processes in this very focused book.  Many papers investigate the growing
    field of multilayer packaging, detailing the compatibility of various
    materials.  Also included in this volume are papers on polymer and 
    non-ceramic packaging materials" (From ACS bulletin)

   Note:  This book contains papers from the Third Int. Ceramic Science and
       Technology Congress, San Francisco, CA, Nov. 1-4, 1992.

         The Americal Ceramic Society
         735 Ceramic Place
         P.O. Box 6136
         Westerville, OH 43086-6136
         Tel:  (614) 794-5890
         Fax:  (614) 899-6109

----------------------------------------------------------------------------        
*ITEM 5.2  "Burn-In Testing" 
            by Kececioglu, Sun.  
            Prentice Hall, 250 pges, 1994.  ISBN 0-13-324211-0
----------------------------------------------------------------------------
   "For graduate courses in reliability engineering that has a focus
    on the electronic industry where their form of testint is now
    important" (From Prentice Hall summary)

   Note:  This book contains papers from the Third Int. Ceramic Science and
       Technology Congress, San Francisco, CA, Nov. 1-4, 1992.

----------------------------------------------------------------------------        
*ITEM 5.3  "Physical Design for Multichip Modules" 
            by Sriram and Kang.  
            Kluwer Publishers, 216 pges, 1994.  ISBN 0-7923-9450-X
----------------------------------------------------------------------------
   "Physical Design for Multichip Modules collects a large body of
    recent research work in the area of multichip module (MCM)
   design, including both a survey of published results as well as
   original work by the authors.  All major aspects of MCM
   physical design are discussed, including interconnect analysis
   and modeling, system partitioning and placement, and
   multilayer routing." (From Kluwer advertisement)

   Chapter 1:  Introduction
   Chapter 2:  Analysis and modeling of MCM interconnects
   Chapter 3:  System partitioning and chip placement
   Chapter 4:  Multilayer MCM routing
   Chapter 5:  Performance-oriented tree construction
   Chapter 6:  Layer assignment approaches

         Kluwer Academic Publishers
         (617)871-6600         Fax: (617)871-6528
         email: kluwer@world.std.com
         

          
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*                            END OF NEWSLETTER                              *
*                                                                           *
*         PACKAGING AND INTERCONNECTION ELECTRONIC NEWSLETTER               *
*                                                                           *
*                          Volume 1, Number 3                               *
*                           August 24, 1994                                 *
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