Volume 2, Number 1
January 30, 1995
- RESOURCES: None this issue
- CALENDAR OF CONFERENCES/MEETINGS
- 4th International Conference & Exhibition on Multichip Modules
April 19-21, 1995. Radisson Hotel, Denver, Colorado, USA
- 17th International Electronics Manufacturing Symposium
Oct, 2-4, 1995. Hyatt Hotel, Austin TX USA
- Workshop on Interconnections within High Speed Digital Systems
May 14-17, 1995. Ploacho Plaza Hotel Santa Fe, New Mexico, USA
- First International Symposium on Advanced Packaging materials
Feb. 7-9, 1995. Stouffer Waverly Hotel, Atlanta, Georgia,USA
- INTERpack '95
March 26-30, 1995, Westin Maui Resort, Lahaina, Hawaii USA
- PCB Design Conference
March 21-23, 1995, Convention Center, Santa Clara, CA USA
- 1995 Japan International Electronic Manufacturing Technical Symposium
December 4-6, 1995, Omiya, Saitama Japan
- Industry Assessment Workshop: Assembly and Packaging
March 9-10, 1995, Harvey Hotel and Dulles-Fort Worth Airport
- 25th European Solid State Device Research Conference (ESSDERC'95)
September 25-27, 1995, The Hauge, The Netherlands
- VLSI Packaging Workshop: Spotlight BGA
October 16-18, 1995, Hyatt Regency, Monterey, California USA
- Simulation and Design of Microsystems and Microstructures
September 26-28, 1995, Southampton, United Kingdom
- TC-6 NEWS
- COURSES
- Surface Mount Technology: Keys to Successful Implementation
March 20-22, 1995 Santa Clara, CA
June 14-16, 1995 Hartford, CT
- Advanced Microelectronics Assembly Technology
Reliability & Yield Issues of Materials, Die attach, plastic
molding, and wire bonding
February 6-9, 1995, Dallas Grand Hotel, Dallas Texas
- RECENT BOOKS
SCHEDULE OF CONFERENCES/MEETINGS
April 19-21, 1995
Radisson Hotel, Denver, Colorado, USA
Sponsers: ISHM, IEPS, EIA, IEEE-CPMT
- General Chair
- General Chair Elect
- W. Kinzy Jones, Florida Int'l University
- Technical Cochairs:
- Phillip Garrou, Dow Chemical Co.
- Paul R. Van Loan, Hewlett Packard
For registration/program information,
call (800)535-ISHM or fax (703)758-1066.
Wednesday, April 19, 1995 Sessions.
Session WA1: Military and Space
Session WA2: MCM-L Technology
Session WA3: MCM-C Technology
Session WP1: Automotive Applications
Session WP2: Diamond Technology
Session WP3: Modeling and Analysis
Session WP4: Thin Film Processes
Thursday, April 20 Sessions.
Session THA1: Low Cost MCM Manufacturing
Session THA2 Interconnections
Session THA3: Laser and Materials Technology
Session THP1: Thin Films: Structure and Applications
Session THP2: Design and Test
Session THP3: Known Good Die
Friday, April 21 Sessions.
Session FA1: Telecom Applications
Session FA2: Dielectrics and Processing
Session FA3: MCM-L Applications.
PROFESSIONAL DEVELOPMENT COURSES (April 18: 9 am - 5 pm)
Course TA: Multichip Modules: The Fundamentals
(R. Wayne Johnson, Auburn Univ.)
Course TB: Thermal Management of Multichip Modules
(Charles Minning, Hughes Aircraft)
Course TC: PCMCIA: Successful Design & Manufacture
(Charles Bauer, TechLead & Happy Holden, HP)
Return to Conference Listing
Oct, 2-4, 1995
Hyatt Hotel, Austin TX USA
Sponsers: IEEE CPMT, EIA
General Chair Program Chair
Walt Trybula D. Maillard
SEMATECH Rensselaer Polytechnic Inst.
Austin, TX Troy, NY
Tel: (512)356-3306 Tel: (518)276-6724
Fax: (512)356-3525 Fax: (518)276-2990
Email: walt.trybula@sematech.org
don_millard@dmi.rpi.edu
Japan Liason Taiwan Liason Europe Liason
Takaaki Ohsaki Li-Chung Lee Michel Salagoity
NTT ITRI Solectron France
Tokyo, Japan Hainchu, Taiwan Cestas, France
Tel: 81-422-59-2511 Tel: 886-35-916800 Tel: 33-56-757470
Fax: 81-422-59-2164 Fax: 886-35-820247 Fax: 33-56-898136
EMAIL: mika@aela.ntt.jp
The International Electronics Manufacturing Technology (IEMT) Symposium
is an international forum for the presentation of research, development,
and application of technologies and systems for use in the manufacture
of electronic components, assemblies, and systems. The IEMT Symposia
normally are held twice each year: each autumn in the United States and
each spring alternating between Europe and Japan.
TOPICS OF INTEREST
*Integrating Design and Manufacturing
- Agile manufacturing
- Applied concurrent engineering & cycle time reduction
- Design for manufacturability, profit, the environment, etc.
- Concurrent engineering CAD/CAM tools and frameworks
- Intelligent manufacturing (AI, neural nets, closed loop control)
*Reducing Manufacturing Cost and Cycle Time
- Low cost, high volume manufacturing
- Use of multimedia (3D imaging, interface design, virtual reality)
- Self-test and burn-in
- Improving and reducing the requirement for inspection
- Improving quality and process control
* Advanced Interconnect Development
- Displays, computers, telecommunications, handheld products
- Multichip modules and ball grid arrays
- Fine pitch interconnect improvements and alternatives
- Applied photonics and electro-optics
- Advanced packaging (3-D pkg, flexible pkg, COB, COG)
*Manufacturing Operations Improvement
- CFC elimination, PB-free soldering
- Equipment engineering, automation, CIM
- JIT system development and implementation
- Shop floor scheduling and operation
- Optimizing semiconductor manfacturing
*Manufacturing Analysis
- Statistical methods in manufacturing
- Joint reliability & mechanical properties management
- Manufacturing management practices and science
- Placement sequence optimization
- Manufacturing tool, equpment, process modeling and reliability.
ABSTRACT SUBMISSION
To submit a paper, send an abstract of at least 250 words by March 17,
1995 to:
Terry Chappell, Publications
730 Encino Drive
Aptos, CA 95003 USA
Voice and fax: 408-662-1936
EMAIL: tnchappell@aol.com
The abstract must clearly describe the nature, scope, content,
organization, key points and significance of the proposed paper.
The paper must consist of work or results not published previously.
Submission of an abstract represents a commitment to submit a cleared
manuscript by June 30, 1995. It also represents a commitment to either
attend the conference or send a knowledgable substitute who can
answer questions regarding the reported work. It is the author's
responsibility to obtain internal company approval consistent with
these deadlines.
AUTHOR NOTIFICATION
Authors will be notified of paper acceptance, with full instructions
for publication, by April 24, 1995. Camera-ready manuscripts are
expected to be from three to eight pages, including diagrams,
figures, and photographs.
Return to Conference Listing
May 14-17, 1995
Ploacho Plaza Hotel
Santa Fe, New Mexico
Sponsored by: IEEE LEOS in cooperation with IEEE Computer
and IEEE Communications Societies.
WORKSHOP SCOPE
The rapid evolution of intergrated circuit technology has led to
dramatic improvements in the performance of advanced computing
and communications systems. Future applications will require
even more computational and communications power. Even in today's
systems, however, interconnections are often a bottleneck to
achieving higher performance. The purpose of this workshop is to
determine the interconnection requirements of emerging computer
and communications systems and to evaluate advanced interconnection
technologies in light of those requirements. Because of the
interdisciplinary nature of the problem, the workshop brings together
researchers and practitioners with expertise in a variety of fields
including electrical and optical interconnection technology,
advanced system architectures, and the algorithms and applications
implemented in these systems.
INFORMATION:
To obtain information about contributing topics/papers for
presentation, please contact:
Rick Lytel
Akzo Nobel Electronic Products Inc.
250 C Twin Dolphin Drive
Redwood City, CA 94065
Fax: 415-508-2959
Email: lytel@akzochip.com
To be placed on the mailing list to receive further details about the
workshop, please contact:
IEEE/LEOS
445 Hoes Lane
PO Box 1331
Piscataway, NJ 08855-1331
Phone: 908-562-3894
Fax: 908-562-8434
Email: s.phillips@ieee.org
Return to Conference Listing
First International Symposium on Advanced Packaging Materials
Feb. 7-9, 1995
Stouffer Waverly Hotel
Atlanta, Georgia USA
Sponsored by: IEEE CPMT and ISHM.
General Chair
Rao R. Tummala
Georgia Inst. of Technol.
Atlanta, Georgia USA
This symposium is devoted to recent advances made in electronic
packaging materials. Symposium attendance will be valuable to
developers, producers, and users of substrates, advanced PC
boards, single chip packages, multichip modules, optoelectronic and
display packages.
Tuesday, Feb. 7 (2:30 pm - 4:30 pm)
* Session I: Chip-to-substrate interconnection materials
Wednesday, Feb. 8
* Session II: Ceramic packaging materials
* Session III: Integrated passive component materials
* Session IV: Thermal management materials
* Session V: Optoelectronic materials
Thursday, Feb. 9
* Session VI: Display materials
* Session VII: Advanced organic boards
* Session VIII: Polymer dielectrics
* Session IX: Plastic package and encapsulation materials
REGISTRATION INFORMATION: Telephone (800)535-ISHM or (703)758-1060.
Return to Conference Listing
INTERpack '95
March 26-30, 1995
Westin Maui Resort
Lahaina, Hawaii USA
Sponsored by: ASME
In cooperation with: JSME, IEPS, and IEEE
REGISTRATION AND DETAILED PROGRAM INFORMATION:
Ms. Marisa Scalice, Meetings Manager
ASME (American Society of Mechanical Engineers)
New York, NY
Tel: 212-705-7793 Fax: 212-705-7856
Monday, March 27 (9:30-11:45 am)
* Session: Packaging applications in telecommunications
* Session: Packaging CAD - tools and systems
* Session: Packaging education
* Session: Compuational techniques in packaging design I
* Session: Convective cooling of electronic packages I
* Session: Modeling solder joint reliability
Monday, March 27 (1:30-3:25pm)
* Session: Packaging design methodology I
* Session: Computational techniques in packaging design II
* Session: Convective cooling of electronic packages II
* Session: Solder joint fatigue under thermal cycling
* Session: Plastic packaging I
Monday, March 27 (3:40-5:45pm)
* Session: Packaging design for multichip modules
* Session: Thermal conduction in electronic packaging I
* Session: Solder joint reliability I
* Session: Structural analysis of packages, PCBs, & modules
* Session: Plastic packaging II
* Session: Testing/inspection of packages, PCBs/optical fibers
Tuesday, March 28 (8:00-9:10am)
* Keynote: Dr. Kenneth Flamm, PDASD, Advanced Research Projects Agency
"US Technology Policy for Flat Panel Displays"
Tuesday, March 28 (9:30-11:45am)
* Session: Automotive and power electronics
* Session: Packging design methodology II
* Session: Structural analysis of IC interconnects
* Session: Thermal conduction in electronic packages II
* Session: Optoelectronics (panel session)
* Session: Solder joint reliability II
Wednesday, March 29 (8:00-9:10am)
* Keynote: Dr. Ken-Ichi Matsumo: Director MEL, MITI Japan
"Intelligent Manufacturing Systems"
Wednesday, March 29 (9:30-11:45am)
* Session: Micromechanics
* Session: Material characterization - Adhesives
* Session: Manufacturing and assembly - chip interconnections
* Session: Physics of failure in electronic packaging
* Session: Thermal design methodology for electronic components
Wednesday, March 29 (1:45-3:30 pm)
* Panel Session: International Developments in Packaging Technology
Wednesday, March 29 (1:45-4:45 pm)
* Tutorial: Acoustic micro imaging for process control of plastic ICs
* Tutorial: Design and application of silicon piezoresistive stress
stress sensors in electronic packaging
* Tutorial: Moire interfermometry as a tool
Wednesday, March 30 (8:00-9:10am)
* Keynote: Dr. Robert Hannemann: Digital Equipment Corp.
"Mobile Computing"
Thrusday, March 30 (9:30-11:45am)
* Session: Computer Packaging (Panel)
* Session: Material characterization - solders
* Session: Manufacturing & assembly - thermofluid considerations
* Session: Plastic packaging - delamination
* Session: Thermal management of multichip modules
* Session: Experimental determination of CTE and thermal stress
Thrusday, March 30 (1:30-3:30pm)
* Session: Thermostructure characterization of packaging materials
* Session: Manufacturing and assembly of electronic systems
* Session: Phase-change cooling of electronic components
* Session: Experimental determination of packaging behavior
Return to Conference Listing
March 21-23, 1995
Convention Center
Santa Clara, CA USA
INFORMATION: Contact Marcia Gulino (415-905-2354)
Return to Conference Listing
December 4-6, 1995
Omiya, Saitama Japan
Sponsored by IEEE CPMT
INFORMATION: Contact
USA:
E. Jan Vardaman (USA Liaison)
TechSearch International, Inc.
PO Box 200295
Austin, Texas 78720-0295
Tel: (512)343-4508
Fax: (512)343-4509
Europe:
Jean Joly (Europe Liaison)
VLSI Packaging Development
Rue Jean Jaures-B.P. 68-78340
Les Clayes-sous-bois France
Tel: (1)30 80 77 88
Fax: (1)30 80 78 33
Japan and Far East:
Nubuo Iwase (Chairperson)
Materials and Devices Development Center
Toshiba Corp.
2-4 Suehiro-cho, Tsunumi-ku
Yokohama 230, Japan
Tel: +81-45-510-5200
Fax: +81-45=500=2549
As international forums for the presentation of research results,
recent developments, and the application of technology and systems
used in the manufacture of electronic components and the assembly
of systems, these symposia are held twice a year. The 1995 Japan IEMT
Symposium will mark the 18th in the series and the 5th staged in Japan.
The purpose of the event is to share knowledge and experience as derived
from the laterst research and development in the realm of electronic
technology.
The technical program committee has launched its call for original papers
covering a wide spectrum of topics, not only manufacturing technology
and systems but also new developments as applying to modules, devices,
components, and related materials.
MAJOR TOPICS
Manufacturing
- Computer integrated manufacture (CIM)
- Automated manufacturing technology including robotics
- Fine pitch surface mount technology
- In-process inspection and testing
- Process equipment diagnosis
Packaging Technology
- Multi-chip modules (MCMs)
- High-speed, high-frequency modules
- design and simulation
- Notebook, laptop, workstation and mainframe computers
- Approach to portable telephone, IC card, and personal data
assistance (PDA) for multimedia electronics
Optoelectronics Technology
- Optical measurement and sensing, image processing for
manufacturing technology
- Optical interconnection module
- Optical communication component and module
- Display device and sensor
- Optical disc and printer
Device, Component and Applications
- Multi-functional device
- Surface mount device (SMD)
- Sensing and printing device
- Micro-machining and applications
- New applications of thin film technology
- Failure analysis and reliability
Material and Process
- Substrate and PCB
- Organic and inorganic material
- Microinterconnection: TAB, flip chip, micro pin, anisotropic
conductive film (ACF), etc.
- Soldering and cleaning
- New material and process for eliminating chlorofluoro carbon
PAPER SUBMISSION
An abstract, not to exceed 500 words in length, which clearly describes
the nature, purpose, scope, content, organization, and key points of
the proposed paper is required for paper selection and paper
assignment. Figures or tables which support the abstract may be
attached but doing so is not necessary. The official language of
the Symposium is English. All papers and presentations must be in
English.
The abstract (+ five copies) bearing the name, address and tel/fax/telex
numbers of the principal author must be sent to reach the secretariat
not later than March 3, 1995.
Notification of paper acceptance will be mailed by June 14, 1995. The
photo-ready manuscript should be received at Secretariat no later than
September 4, 1995.
Please address all correspondence to
Secretariat of 1995 Japan IEMT Symposium
c/o International Communications specialists, Inc.
Kasho Bldg., 2-14-9, Nihombashi, Chuo-ku, Tokyo, JAPAN
Return to Conference Listing
March 9-10, 1995
Harvey Hotel and Dulles-Fort Worth Airport
Sponsored by: EIA Multichip Module Division
INFORMATION: Call Eric Samuelson at (703)907-7546 for details
or to register. For hotel information, call Harvey's
at (214)929-4500.
REASON:
The MCM Division of EIA is dedicated to the improvement of the
Direct Chip Attach (DCA) industry infrastructure in the United
States. While there are many symposia for technology forecasting
and the presentation of cutting edge developments, the industry
has no forum for a "snapshot" assessment of current capabilities.
The goal of his first, quarterly Industry Assessment Workshop is
to develop an understanding of the U.S. manufacturing capabilities
for advanced packaging among all levels of the electronics industry.
As former technology "showstoppers" become mature manufacturing
technologies, there is a real need for comprehensive overview of
the resources available to US manufacturers.
METHOD:
The real issues for advanced packaging today include
assembly/packaging, substrates/interconnect, design, and known good
die. Assembly and packaging will be covered during the March
meeting, addressing wirebonding, dispense and cure, pick and place,
flip chip, and TAB. For each of the subjects, a representative
of the manufacturing industry will present the issues that they see
as the major shortcomings of the equipment and materials available.
They will be followed by representatives from the suppler community
for that technoloigy who will give a brief description of their
company's product capabilities. A short roundtable discussion will
follow.
RESULTS:
One of the tangible results of the program will be an industry wide
directory of current products and services. "State of the Market"
reports will be distributed after each session based on presentations
and data sheets. Manufacturers will use these reports as a baseline
for understanding available technology and the government will be able
to use them to understand the strengths and weaknesses of the US
infrastructure.
COST:
Cost for participation will be $350 and include the resulting Industry
Assessment, a summary of presentations and product data sheets for
participating companies. Cost to EIA MCM Dvision members is $95.
All are welcome to attend
Return to Conference Listing
September 25-27, 1995
The Hauge, The Netherlands
INFORMATION:
Secretariat ESSDERC'95
Van Namen & Westerlaken
P.O. Box 1558
NL-6501 BN NIJMEGEN, The Netherlands
Tel: +31 80 23 44 71
Fax: +31 80 60 11 59
Email: essderc@et.tudelft.nl
To keep updated on ESSDERC'95, send an empty email message (no
subject required) to essderc@visivie.tuwien.ac.at and you will
receive the latest information.
SUMMARY
ESSDERC'95 will be the 25th in a series of annual meetings devoted
to the physics, technology, and characterization of solid state
devices. The themes of interest also include packaging and
interconnects issues:
* Interconnect systems for multilevel metalization (under the
main theme: silicon integrated circuit technology)
* Interconnect and packaging modeling (under the main
theme: Modeling, characterization and reliability)
* Packaging: bump and flip-chip technology, I/O count
packages, thin packages (smart cards), multichip
modules, new packaging concepts.
* Special topics: Interconnect technology
SUBMISSION OF ABSTRACTS
The deadline for submission of contributed abstracts (2 pages)
is March 24, 1995.
Return to Conference Listing
October 16-18, 1995
Hyatt Regency, Monterey, California USA
Sponsored by IEEE CPMT, NIST
INFORMATION
Program Chair: General Chair:
Bill Hamburgen Elain Pope, MS: CH5-137
Digital Equipment Corporation Intel Corporation
250 University Avenue 5000 W. Chandler Blvd.
Palo Alto, CA 94301 Chandler, AZ 85226
Tel: (415)617-3329 Tel: (602)554-5368
Fax: (415)617-3374 Fax: (602)554-7945
Email: billh@pa.dec.com Email: d_elaine_pope@ccm.hf.intel.com
DESCRIPTION
The VLSI Packaging Workshop has been run for over 15 years as a program
of the IEEE Components, Packaging, and Manufacturing Technology Society's
Technical Committee on Packaging (TC-6), with co-sponsorshop from the
National Institute of Standards and Technology. The committee members,
speakers, and workshop attendees represent a braod spectrum of the
international computer and electronics industries and universities.
Attendance at the workshop is limited to foster discussion and technical
interaction, aiming to attract participants -- not an audience.
Attendance by individuals from a single company is limited to ensure a
wide representation and participation across the industry. The workshop
attendees will be senior technical people from a wide variety of
engineering disciplines world wide.
There will be 25 half-hour presentations in 5 plenary sessions.
The 1995 workshop will focus on BGA packaging solutions and issues,
although other packaging technologies will not be excluded.
BGA TOPICS will include
* High performance, high speed packaging
* Thermal performance enhancement
* Materials
* Design rules and models
* Chip and board interconnect processes
* Manufacturability and process control techniques
* Quality and reliability
OTHER TECHNOLOGIES
* Known good die
* Multi-chip modules (MCM)
* High frequency packaging
* Others...
PAPER SUBMISSION
A hard copy of a one to four page abstract, including up to 4
of your most important figures, should be sent by April 12, 1995
to either the program or general chair listed above.
Return to Conference Listing
September 26-28, 1995
Southampton, United Kingdom
INTRODUCTION:
Rapid advances have been made in the technology for the manufacture
of microsystems and microstructures in recent years. These major
advances and the development of micro electro mechnanical systems
has created a demand for accurate design and simulation systems which
can be used to predict the performance of the systems and the
behavior of the fabrication and manufacturing process. As the
fabrication of prototypes is very expensive, simulation of the
device properties in the design phase is of great importance.
The design of microstructures can be greatly enhanced by using
simulation technology. Not only can the microsystem be improved, but
also, the production process can be optimised. The physical phenomena
affecting the design of microsystems and microstructures are many,
ranging from fluid flow around the device, the thermal characteristics
of the device, stress and displacement of cracks, and the general
electrostatic behavior.
TOPICS OF INTEREST INCLUDE (but are not limited to)
Design Simulation and analysis
Optimisation Material modeling
Fabrication processes Manufacturing processes
Correlation and experiments Integration
CAD Measurement problems
APPLICATION AREAS such as
Microelectronics Mechatronics
Microelectromechanical systems Medicine and biology
Engineering, automotive, aerospace Transducers
Computers and information processing Environmental
CALL FOR PAPERS
Papers are invited on the topics indicated above and others falling
within the scope of the conference. Three copies of an abstract
of not more than 300 words, clearly stating the purpose, results
and conclusion of the work to be descibed in the final paper should
be submitted to the Conference Secretariat by February 20, 1995. Each
abstract should clearly state the most relevant conference topic to
the submitted abstract.
Sue Owen, Conference Secretariat
Wessex Institute of Technology
Ashurst Lodge, Ashurst, Southampton
S040 7AA, United Kingdom
Tel: 44 0 1703 293223
Fax: 44 0 1703 292853
Email: CMI@ib.rl.ac.uk
Return to Conference Listing
Return to Index
IEEE CPMT NEWS
A new 2-1/2 hour videotape ("Future Impact of New Technology")
recorded at the IPC conference in October 1994 is available.
The tape features a group of industry leaders, associated in the consulting
activities of Interconnection Decision Consulting: Jack Balde,
Wulf Knausenberger, George Messner, Gene Shapiro, and Don Wilson.
For ordering information (Video Order #VT-EP), contact IPC at
Tel: (708)677-2850
Fax: (708)677-9570
Return to News Listing
Return to Index
COURSES
March 20-22, 1995 Santa Clara, CA
June 14-16, 1995 Hartford, CT
INFORMATION
This three day tutorial is designed to provide a broad exposure to
state-of-the-art SMT design, processing, assembly, and test concepts.
DAY 1 - AM: Board design and layout guides for manufacurability
Day 1 - PM: Board fabrication and printing
Day 2 - AM: Component attachment and robotic assembly
Day 2 - PM: Soldering
Day 3 - AM: Cleaning
Day 3 - PM: Quality and repair
CONTACT:
Center for Continuing Engineering Education
College of Engineering and Applied Science
University of Wisconsin at Milwaukee
929 North Sixth Street
Milwaukee, WI 53203
Tel: (414)227-3200
Fax: (414)227-3146
Return to Courses Listing
February 6-9, 1995
Dallas Grand Hotel, Dallas Texas
INFORMATION
This comprehensive three and a half day program will address the
major issues relating to reliability and yield in wire bonding
and plastic encapsulation. Coverage includes: testing, intermetallic
reactions, bond failures, cleaning methods, mechanical problems,
and types and applications of die bonding. A one day overview
of materials and material properties necessary to understand the
above material will begin the program.
Contact:
Engineering Professional Development
Box 9 Harvill Building, Room 235
Second and Olive Street
University of Arizona
Tucson, AX 85721
Tel: (602)621-3054
Fax: (602)621-1443
PROGRAM
Monday: May 6, 1995
* Introduction to materials used in microelectronics assembly
* Mechanical properties of materials
* Phase diagrams and microstructural development
* Surfaces and interfaces
* Corrosion and degradation of materials
Tuesday: May 7, 1995
* Introduction to solder bonding
* Methods of bond evaluation
* Elements of solder bonding
* Molded plastic packages
* Overview of process. die attach + wire bond + transfer molding
* Die attach adhesives and process
* Epoxy molding compounds and molding process
* Reliability and failure mechanisms
* Automated, on line assembly
* New adhesive types and forms.
Wednesday: May 8, 1995
* Other IC package types
* Circuit board assembly
* Multichip modules
* Silicone gels and coatings
* Military hybrids, hermetic metal packages
* Plastic cavity packages
* RF and other high heat packages
* CERDIPs and other ceramic packages
* Wire bond testing
* Intermetallic compounds
* Bond failures resulting from plating impurities
Thursday: May 9, 1995
* Cleaning to imporve bondability and reliability
* Cratering in silicon and gallium arsenide
* Mechanical problems in wire bonding
* Assessng reliability of new bonding mettalurgy
* The right way to choose a new bonding technology
* Other extended topics.
Return to Course Listing
Return to Index
BOOKS
Author: G.L. Ginsberg,and D.P. Schnorr
Publisher: McGraw Hill (1994)
290 pages $55
SUMMARY: From EP&P Description
With an emphasis on materials, processes, and applicaitons,
this book covers the considerations associated with MCM-C
MCM-D and MCM-L as well as other related technologies. It is
intended for use as a text for college or graduate study; for
design, fabrication, and process engineers; for managers planning
new or alternate technology; and for the marketing and sales people
who need a practical understanding of MCMs.
Chapter 1 overviews electronic packaging driving forces, including
costs, IC fabrication, performance, and substrate price vs density.
Overall considerations for MCM packages, basic elements of MCM
packages, bare die termination techniques, and design considerations
are covered in chapters 2 through 5. Chapters 6, 7, and 8 cover
the MCM-C, MCM-D, and MCM-L package types. The final chapters
cover supplemental interconnection devices, thermal design
considerations, and MCM applications.
Return to Book Listing
Author: D.R. Frear, et al (Editors)
Publisher: Van Nostrand Reinhold (1994)
418 pages $70
SUMMARY: From EP&P Description
This book details the four basic parameters essential for implementing
a computational solder interconnect system model. The parameters are
response of each material in the assembly, geometry of the assembly,
loading conditions, and boundary conditions.
Chapter 1 provides an overview. Chapter 2 discusses the basic
material properties of solder alloys including their metallurgical
aspects and mechanical response in test environments. Formation,
importance and mechanical properties of intermetallics and
interface materials are presented in chapter 3. Chapter 4 details the
constitutive models of solder alloys. Chapter 5 discusses methods
for predicting the shape of the joint from the melt. Chapter 6
discusses solder interconnect thermomechanical modeling, including
geometry approximations, boundary conditions, loading considerations,
and modeling techniques. Chapter 7 covers lifetime prediction through
accelerated testing techniques. Chapters 8 and 9 describe through-
hole solder moint, surface mount solder moint and multichip module
applications.
Return to Book Listing
Author: John H. Lau (Editor)
Publisher: McGraw Hill ISBN 0-07-036608 (1995)
612 pages
CONTENTS:
Chp 1: Brief introduction to ball grid array technologies
Chp 2: Ceramic substrates for ball grid array packages
Chp 3: Plastic substrates for ball grid array packages
Chp 4: Printed circuit board routing considerations for BGA
Chp 5: Overview of ceramic ball and column grid array packaging
Chp 6: Ceramic ball grid array assembly
Chp 7: Thermal and electrical management of ceramic ball grid
array assembly
Chp 8: Reliability of ceramic ball grid array assembly
Chp 9: Plastic ball grid array packaging technology
Chp 10: Plastic ball grid array assembly
Chp 11: Thermal and electrical performance management in plastic
ball grid array packages from the vendor's perspective
Chp 12: Thermal and electrical management of plastic BGA packages -
A user's perspective
Chp 13: Reliability of plastic ball grid array assembly
Chp 14: Area tape automated bonding ball grid array technology
Chp 15: Inspection of ball grid array assembly
Chp 16: Rework of ball grid array assemblies
Chp 17: Burn in sockets for ball grid arrays (BGAs)
Chp 18: BGA infrastructure
Chp 19: Packaging glossary
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Author: John H. Lau (Editor)
Publisher: Van Nostrand Reinhold ISBN 0-442-01441-4 (1994)
545 pages
CONTENTS:
Chp 1: A brief introduction to wire bonding, tape automated bonding,
and flip chip on board for multichip module applications
Chp 2: Making COB testing tractable: Chip pretest and system
diagnostics
Chp 3: Chip level interconnect: Wire bonding for multichip modules
Chp 4: Chip level interconnect: Wafer bumping and inner lead bonding
Chp 5: Chip level interconnect: Solder bumped flip chip
Chp 6: Chip attachment
Chp 7: Wire bonding chip on board
Chp 8: Tape automated bonding chip on board and MCM-D
Chp 9: Solder bumped flip chip attach on SLC board and multichip module
Chp 10: Micron bump bonding chip on board
Chp 11: Chip on board encapsulation
Chp 12: Underfill encapsulation for flip chip applications
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Author: John H. Lau (Editor)
Publisher: Van Nostrand Reinhold ISBN 0-442-00427-3 (1992)
630 pages
CONTENTS:
Chp 1: A brief introduction to tape automated bonding
Chp 2: Electrical performance of tape automated bonding
Chp 3: First-level packaging costs: Tape bonding versus
other high-lead package options
Chp 4: Maaterials choices for tape automated bonding
Chp 5: TAB tape design and manufacturing
Chp 6: Wafer bumping
Chp 7: TAB inner lead bonding
Chp 8: TAB testing and burn-in
Chp 9: TAB encapsulation
Chp 10: TAB outer lead bonding
Chp 11: Equipment selection for TAB outer lead bonding
Chp 12: TAB inspection and rework
Chp 13: TAB thermal management
Chp 14: Reliability aspects of tape automated bonding
Chp 15: Multichip packaging with TAB
Chp 16: Interconnection substrates for TAB devices
Chp 17: TAB developments and trends in Europe
Chp 18: TAB developments and trends in Japan
Chp 19: TAB implementation: A case study in the military environment
Chp 20: TAB implementation: A case study in the commercial environment
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Author: John H. Lau (Editor)
Publisher: Van Nostrand Reinhold ISBN 0-442-01258-6 (1994)
630 pages
CONTENTS:
Chp 1: A brief introduction to fine pitch surface mount technology
Chp 2: Fine pitch packaging for surface mount
Chp 3: Solderability of fine pitch surface mount components
Chp 4: Substrate materials and design for fine pitch technology
Chp 5: Fine pitch soldering and solder pastes
Chp 6: Screen and stencil printing technology for fine pitch assembly
Chp 7: Pick and place technology for fine pitch assembly
Chp 8: Estimation of solder volume
Chp 9: Vapor phase solder reflow for fine pitch assembly
Chp 10: Convection/infrared and convection dominant reflow soldering
of fine pitch SMT devices
Chp 11: Forced convective solder reflow for fine pitch assembly
Chp 12: Nitrogen-based solder reflow for fine pitch assembly
Chp 13: Pulsed thermode hotbar bonding
Chp 14: Aqueous and semiaqueous cleaning of fine pitch assemblies
Chp 15: NonCFC cleaning (No-Clean) of fine pitch assemblies
Chp 16: Inspection of fine pitch assemblies
Chp 17: Surface mount repair
Chp 18: Total quality management (TQM) and statistical process
control (SPC) for fine pitch assembly
Chp 19: Thermal management of fine pitch assemblies
Chp 20: Electrical testing of bare fine pitch printed circuit boards
Chp 21: Reliability aspects of fine pitch assembly
Chp 22: Technical management issues of fine pitch technology
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Author: John H. Lau (Editor)
Publisher: Van Nostrand Reinhold ISBN 0-442-01058-3 (1993)
870 pages
CONTENTS:
Chp 1: Thermomechanivs for electronics packaging
Chp 2: Thermal expansivity and thermal stress in multilayered
structures
Chp 3: Thermal stresses in anisotropic multilayered structures
Chp 4: Transient thermal stresses in multilayered devices
Chp 5: Temperature dependence of thermal expansion of materials
for electronics packages
Chp 6: Thermal stress considerations in die-attachment
Chp 7: Die stress measurement using piezoresistive stress sensors
Chp 8: Analysis of the thermal loading on electronics packages by
enhanced moire interferometry
Chp 9: Correlation of analytical and experimental approaches to
determination of thermally induced printed wiring board
(PWB) warpage
Chp 10: Thermal stress-induced open-circuit failure in microelectronics
thin-film metallizations
Chp 11: Thermal stress and stress-induced voiding in passivated narrow
line metalizations on ceramic substrates
Chp 12: Predicted bow of plastic packages of integrated circuit
(IC) devices
Chp 13: Thermal and moisture stresses in plastic packages
Chp 14: Solutions to moisture resistance degradation during solder
reflow of plastic surface mount components.
Chp 15: Thermomechanical fatigue of 63SN-37Pb solder joints
Chp 16: A prediction of the thremal fatigue life of solder joints using
crack propagation rate and equivalent strain range
Chp 17: Microstructural evaluation of SnPb solder and Pd-Ag thick-film
conductor metalization under thermal cycling and aging conditions
Chp 18: Solder joint reliability of leadless chip carriers
Chp 19: Solder creep-fatigue interactions with flexible leaded surface
mount components
Chp 20: Thermal stress issues in plated-through-hole reliability
Chp 21: Nonlinear analysis of a ceramic pin grid array (PGA) soldered
to an orthotropic epoxy substrate
Chp 22: Mechanics of wirebond interconects
Chp 23: Corrosion in microelectronics packages
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Author: John H. Lau (Editor)
Publisher: Van Nostrand Reinhold ISBN 0-442-00260-2 (1991)
630 pages
CONTENTS:
Chp 1: Flux reactions and solderability
Chp 2: Solder paste technology and applications
Chp 3: Technical considerations in vapor phase and infrared
reflow processes
Chp 4: Optimizing the wave soldering process
Chp 5: Post-solder cleaning considerations
Chp 6: Scanning electronic microscopy/energy dispersive X-ray
(SEM/EDX) characterization of solder-solderability and
reliability
Chp 7: The role of microstructure in thermal fatigue of Pb-Sn solder
joints
Chp 8: Microstructure and mechanical propoerties of solder alloys
Chp 9: The interaction of creep and fatigue in lead-tim solders
Chp 10: Creep and stress relaxation in solder joints
Chp 11: Effects of strain range, ramp time, hold time, and temperature
on the isothermal fatigue life of tin-lead solder alloys.
Chp 12: A damage integral methodology for thermal and mechanical
fatigue opf solder joints
Chp 13: Modern appraches to fatigue life prediction of SMT solder joints
Chp 14: Predicting thermal and mechanical fatigue lives from isothermal
low cycle data
Chp 15: Static and dynamic analysis of surface mount component leads
and solder joints
Chp 16: Integrated matrix creep: Application to accelerated testing
and lifetime prediction
Chp 17: Solder joint reliability, accelerated testing, and result
evaluation
Chp 18: Surface mount attachment reliability and figures of merit for
design for reliability
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Author: D. Frear, S.N. Burchett, H.S. Morgan,
and John H. Lau (Editors)
Publisher: Van Nostrand Reinhold ISBN 0-442-01505-4 (1994)
420 pages
CONTENTS:
Chp 1: Introduction: The mechanics of solder allow interconnect
Chp 2: Microstructural influences on the mechanical properties of solder
Chp 3: Interfaces and intermetallics
Chp 4: Constitutive models
Chp 5: Prediction of solder joint geometry
Chp 6: Life prediction and accelerated testing
Chp 7: Thermomechanical modeling of solder joints: numerical
considerations
Chp 8: Applications: through-hole
Chp 9: Surface mount solder joints under thermal, mechanical, and
vibration conditions
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