Volume 2, Number 2
March 10, 1995
- RESOURCES:
- CALENDAR OF CONFERENCES/MEETINGS
- 45th Electronic Components and Technology Conference (ECTC)
May 21-24, 1995. Caeser's Palance, Las Vegas, Nevada
- VLSI Packaging Workshop: Spotlight BGA
October 16-18, 1995. Hyatt Regency, Monterey, California
- 4th Technical Committee on Computer and System Packaging
Spring 1995 Workshop
May 1-3, 1995. Rancho Mirage, California.
- Massively Parallel Processing Using Optical Interconnections
October 23-24, 1995. San Antonio, Texas
- THERMINIC Workshop
International Workshop on Thermal investigations of ICs and Microstructures
September 25-26, 1995. Grenoble, France
- BRASAGE 95: Soldering Technologies
September 20-22. Brest, France
- 12th Annual IEEE SEMITHERM
Twelfth Annual IEEE Semiconductor Thermal Measurement and Management Symposium
March 1996. Austin, Texas
- EUROTHERM Seminar No. 45: Thermal Management of Electronic Systems
September 20-22. Leuven, Belgium
- Plastic Encapsulated Microelectronics Book
- Plastic Encapsulated Microelectronics Short Course
March 15-16, 1995. CALCE Electronic Packaging Research Center, University of Maryland
- International Symposium on Printed Wiring Board Technology
April 18-21, 1995. HKPC Building, Yau Yat Chuen, Kowloon, Hong Kong
- CAll FOR PAPERS - IEEE Multi-Chip Module Conference: MCMC-96
February 5-7, 1996. The Cocoanut Grove, Santa Cruz, CA
A catalog listing several videos (new product and training) along with
books is available from
Catalog Title: IPC Resources: Pathways to Excellence
The Institute for Interconnecting and Packaging Electronic Circuits
7380 N. Lincoln Ave.
Lincolnwood, Illinois 60646-1705
PROGRAM
Caeser's Palance, Las Vegas, Nevada
May 21-24, 1995
The ECTC offers papers covering a wide spectrum of topics, including
not only electronic componenets, but also exciting new developments
in all areas of electronic technologies (e.g. electronics assembly,
packaging, reliability, and materials). In 1995, more than 200
presentations (papers, posters, and short courses) will be presented
by companies, universities, and research institutions from around
the world. The audience will include representatives from a
multitude of universities and companies eager to stay abreast of the
rapidly changing Global Electronics Technology Evolution/Revolution.
The aim of the conference is to contiue to offer quality coverage of
technological innovations in the areas of design, process, materials,
qualtiy, and manufacturing for devices, components, and systems. This
year's program provides insight into numerous technological innovations
that are contributing to the rapidly emerging areas of portable
electronics, flat panel displays, and wireless technologies - just to
name a few. The members of the program committee have expertise in a
wide variety of disciplines and represent many leading universities'
and companies in the electronics industryu. They committed to assembling
the highest quality program for the 45th ECTC!
Detailed Program Announcement and Registration Material
Available from
Jim Bruorton, Publicity Chairman
1995 ECTC
c/o KEMET Electronics Corporation
PO Box 5928
Greenville, SC 29606
Tel: (803)963-6621
Fax: (803) 963-6521
FOLLOWING IS A SMALL SUMMARY OF INFORMATION PROVIDED ON FULL PROGRAM
ANOUNCEMENT
*****************************
PROGRAM SCHEDULE (SESSIONS/COURSES RUN CONCURRENTLY)
Sunday, May 21, 1995 (Morning Courses)
Course 1: Polymers for Electronic Packaging - Materials,
Processes and Reliability.
Course 2: Introduction to Ball Grid Array Technology
Course 3: Advanced Process Integration in Microelectronic
Manufacturing
Course 4: Component Reliability
Course 5: Flip-Chip Solder Bump Technology
Sunday, May 21, 1995 (Afternoon Courses)
Course 6: Ball Grid Array/Flip Chip Techniques - Design for
Reliability
Course 7: Product Reliability and Stress Testing
Course 8: Known-Good Die
Course 9: RF Components in Wireless Communications Systems
Course 10: Low Cost MCMs: Design, Assembly, Packaging, Test,
and Applications
Monday, May 22, 1995 (Morning Sessions)
Session 1: Single Chip Packaging: Ball Grid Arrays (BGAs)
Session 2: Component Processing
Session 3: Wire and Conductive Polymer Interconnect
Session 4: High Density/High Performance E&O Connectors
Session 5: Photonic Packaging Techniques
Monday, May 22, 1995 (Afternoon Sessions)
Session 6: Advances in Single Chip Packaging
Session 7: Component Performance Enhancements
Session 8: Reliability: Design and Testing
Session 9: Electrical Modeling and Simulation
Session 10: VCSEL: Modules and Packaging
Monday, May 22, 1995 (Evening Session)
Session 11: Novel Photonic Packaging I
Tuesday, May 23, 1995 (Morning Sessions)
Session 12: Package Moisture Sensitivity and Die Cracking
Session 13: Fine Line MCMs and Applications
Session 14: Materials: Emerging Technologies
Session 15: Parallel Optical Interconnects
Tueday, May 23, 1995 (Afternoon Sessions)
Session 16: Packaging Design/Architecture
Session 17: 3D MCM/High Density Interconnections
Session 18: Adhesion Technology and Materials
Session 19: Optical Amplifier Hybrid Packaging
OTHER ACTIVITIES - Tuesday, May 23
Poster Presentations
Technology Corner Exhibits
Wednesday, May 24, 1995 (Morning Sessions)
Session 20: Mechanical Modeling/Simulation
Session 21: Manufacturing Technology: BGA Process
Session 22: Materials for Packaging and Interconnections
Session 23: Telecommunications Opto-Device Packaging
Wednesday, May 24, 1995 (Afternoon Sessions)
Session 24: Thermal Simulation and Characterization of Electronic
Packages
Session 25: Flip-Chip Interconnections
Session 26: Manufacturing Technology: Soldering and Encapsulation
Process
Session 27: Novel Photonic Packaging II
ADVANCE REGISTRATION: BEFORE MAY 12, 1995
Registration Rees
$395 - Advance Registration with Proceedings, ECTC and
CPMT luncheons:
$495 - Door registration with Proceedings, ECTC and CPMT luncheons
$300 - Advance Speaker/Session Chair
$400 - Door Speaker/Session Chair
$175 - Speaker one day
$275 - Special Sunday half-day course (AM or PM)
$400 - Special Sunday all-day course
$125 - Students
$300 - Proceedings only (USA postpaid)
$350 - Proceedings overseas.
Return to Conference Listing
CALL FOR PAPERS
IEEE-CPMT and NIST
VLSI Packaging Workshop: Spotlight BGA
October 16-18, 1995
Hyatt Regency, Monterey, California
(Submitted by: Bill Hamburgen billh@pa.dec.com)
The VLSI Packaging workshop, now in its 15th year, is a program of the
IEEE-Components, Packaging Manufacturing Technology Society's Technical
Committee on Packaging (TC-6). Co-sponsorship is provided by the National
Institute of Standards and Technology.
Workshop participants represent a broad international spectrum of engineering
disciplines from commerce and academia. To ensure wide representation and
foster in-depth discussion and technical interaction, attendance is limited.
To encourage a frank exchange on up-to-the-minute findings, there are no
published proceedings, and cameras and tape recorders are not permitted.
There will be 25 half-hour presentations in 5 plenary sessions. The 1995
workshop will focus on BGA packaging solutions and issues, although other
packaging technologies will not be excluded. Topics will include, but are
not limited to:
BGA Design and Manufacturing Other Technologies
- High Performance, High Speed Packaging - Chip Sized Packages
- Thermal Enhancement - MCM
- Materials - Known Good Die
- Design Rules and Models
- Chip and Board Interconnect Processes
- Manufacturability and Process Control
- Quality and Reliability
PAPER SUBMISSION
A hard copy of a one to four page extended abstract - including up to 4 of
your most important figures - should be sent by April 12, 1995 to either:
Program Chair General Chair
Bill Hamburgen Elaine Pope
Digital Equipment Corporation Intel Corporation
250 University Avenue 5000 W. Chandler Blvd.
Palo Alto, CA 94301 Chandler, AZ 85226 MS: CH5-137
Phone: (415) 617-3329 Phone: (602) 554-5368
FAX: (415) 617-3374 or -3375 FAX: (602) 554-7945
billh@pa.dec.com d_elaine_pope@ccm.hf.intel.com
Extended abstracts will be made available to Workshop Participants.
For information on vendor demonstration tables and workshop registration,
please contact:
Paul Baltes, Director
Engineering Professional Development
Box 9, Harvill Bldg Phone: (602) 621-5104
University of Arizona FAX: (602) 621-1443
Tucson, AZ 85721-0076 email: baltes@bigdog.engr.arizona.edu
Up-to-date workshop information can be found on the World Wide Web at:
http://www.research.digital.com/wrl/projects/VLSI_Pkg_Workshop/main.html
Technical Program Committee Members:
Kazumi Allen - Shindo John Lau - HP
Thiam Beng Lim - IME, Singapore Albert W. Lin - ITRI/ERSO, Taiwan
Justin Bolger - Merix Atsushi Nakamura - Hitachi
Ron Gedney - Network 2001 Dennis Olsen - Motorola
George G. Harman - NIST Kanji Otsuka - Meisei U.
Nobuo Kamehara - Fujitsu John Prince - U. Arizona
Jung Ihl Kim - Anam Herbert Reichl - T. U. Berlin
Wulf Knausenberger - AT&T Labs Bill Schmidt - SGI
Yoichi Kohara - Oki Hiroshi Shibata - Mitsubishi
Karel Kurzweil - Bull Toshio Sudo - Toshiba
Teruo Kusaka - NEC
Return to Conference Listing
TECHNICAL COMMITTEE ON COMPUTER AND SYSTEM PACKAGING
SPRING 1995 WORKSHOP
MARRIOTT'S RANCHO LAS PALMAS RESORT AND COUNTRY CLUB
RANCHO MIRAGE, CALIFORNIA
MAY 1-3, 1995
(Submitted by: Howard Davidson Howard.Davidson@eng.sun.com)
The IEEE Computer Society Technical Committee on Computer and System
Packaging invites you to attend the 1995 Spring Workshop.
The program covers a variety of topics of interest to packaging
professionals in the fields of computers, telecommunications, PDA's,
BGA's, MCM's, and core packaging technology.
In accordance with traditions of this workshop, no proceedings are
published. Cameras and tape recorders are not permitted. The level of
technical discussions and exchanges is typically higher than that
experienced at other technical society symposia due to the opportunities
for networking designed into the program. However, proprietary
information is not exchanged.
Due to the limited availability of rooms, the workshop can only
accommodate about 100 attendees and workshop presenters. We are
returning to the Palm Springs area by popular request due to the
excellent response to a previous workshop held there. A brochure on the
resort is included for your reference. This resort combines good
weather, natural beauty, numerous recreational opportunities with very
nice facilities.
The preliminary program is attached. Although quite firm, there may be
a few changes in content or order of presentations by the time of the
workshop. Participants are encouraged to attend the entire workshop
since partial registration fees are not available.
Registration applications should be made prior to April 3, 1995 to
insure a space in the Resort. You are encouraged to circulate this
information to others that you feel are interested in attending the
workshop. We look forward to seeing you at Rancho Mirage. We are
confident that you will enjoy an excellent program in a beautiful desert
and mountain setting.
Your 1995 Workshop Committee
John Nelson
Howard Davidson
Jim Kruchowski
IEEE COMPUTER SOCIETY
TECHNICAL COMMITTEE ON COMPUTER AND SYSTEM PACKAGING
SPRING 1995 WORKSHOP -- RANCHO MIRAGE, CALIFORNIA
SCHEDULE
MONDAY -- MAY 1, 1995
12 noon to 1:00 PM LUNCH
1:30 to 4:30 PM SESSION 1 "PORTABLE COMPUTERS"
Chaired by Robert Hanneman of DEC and Toshio Sudo of Toshiba
"Packaging Technology of TOSHIBA Notebook PC"
Kuniaki Takahashi, Toshiba
"Reliability of Solder Joints on Fine-Pitch Quad Flat-Lead Package for
Notebook PC"
Naoki Nakamura, Fujitsu
"Micropackaging for PCMCIA"
Rob Hannemann, Digital
BREAK
"Portable Packaging Futures"
Rao Tummala, Georgia Tech
"Packaging of Motorola PDAs"
tbd, Motorola
"Sun's First Nomadic Workstation"
Craig Levreault, Sun Microsystems
5:00 to 6:00 PM RECEPTION
6:30 to 7:30 PM DINNER
7:45 to 10:15 PM SESSION 2 "SYSTEM PACKAGING TECHNOLOGY"
Chaired by Paul Wesling of Tandem and Kishore Chakravorty of the
Institute of Microelectronics, NUS.
"Design Comparison with Coplaner Type MCM for Low Cost and Conventional
Type MCM"
Keitarou Yamagishi, Tetsuo Motomiya, and Masayosi Sakao Mistubishi
Electric
"Update of Surface Laminar Circuit and Flip Chip Attach"
Yutaka Tsukada, IBM/Japan Ltd (Yasu)
"Transitioning to High Performance C4/CCGA Packaging"
Matt Nowak, Unisys
"C4 Ceramic Ball Grid Array Packaging and Assembly"
Les Hazlett and Dale Robinson, Motorola Austin
"C4/CCGA Package for H-P High Performance CMOS Processor"
Bill Hannah, Hewlett-Packard
TUESDAY -- MAY 2, 1995
7:00 to 8:00 AM BREAKFAST
8:30 to 11:30 AM SESSION 3 "TELECOMMUNICATIONS TECHNOLOGY"
Chaired by Monica Bakszt of Ericsson and Robert Pfahl of Motorola.
"MCM Applicability In Telecommunication"
Nic De Roose, Alcatel
"Modular DCI Technology Addressed to Cost "
Seppo Pienimaa, Nokia Mobile Phones
"MCM for a 486 Computer Application"
Jan Carlsson, Saab Combitec
"BREAK"
"Low Cost Technology for Opto/Electrical Modules"
Kare Gustafsson, Ericsson Components
"Small Planar Packaging System for High-Speed, High-Density
SwitchingSystems"
Tohru Kishimoto, NTT Network Systems Laboratories
"Packaging of an Optical ATM Switch"
Steve Hinterlong, ATT Bell Laboratories
12 noon to 1:00 PM LUNCH
Afternoon FREETIME
4:30 to 5:30 PM SOCIAL
6:00 to 7:00 PM DINNER
7:00 to 7:30 PM KEYNOTE TALK CMOS vs ECL Mainframes -- "The Rest of
the Story"
Evan Davidson -- IBM
8:00 to 10:00 PM SESSION 4 "MIDSIZE COMPUTERS AND SERVERS"
Chaired by Gordon Robbins of IBM and Philip Conover of Cray Superservers
"Packaging Commodity Microprocessors to Improve System Performance"
Edward C. Priest, Silicon Graphics
"Scaled Common Mode Model: Fast Simulation of Multiline Worst Case
Coupling"
David Quint, Hewlett-Packard
"BGAs in Workstation Applications-A User's Perspective"
Eric Bogatin, Sun Microsystems
"A CFD Study Of A High Performance Impingement Air Heat Sink Design for
Electronic Packages in High-end Workstations And Servers"
S. B. Sathe and B. G. Sammakia, IBM Microelectronics
WEDNESDAY -- MAY 3, 1995
7:00 to 8:00 AM BREAKFAST
8:30 to 11:30 AM SESSION 5 "MAINFRAMES AND PARALLEL PROCESSORS"
Chaired by Lisa Pallotti of Convex and Evan Davidson of IBM
"Packaging Technology for the CMOS Scalable Parallel Supercomputer SX-4"
Jun Inasaka, NEC Corporation
"Packaging of a CMOS ESA/390 Symmetric Multiprocessor"
Frank Almquist, IBM Corporation
"Technology Independent Packaging Model"
Doug Paffel, Cray Research, Inc
"Packaging of the SGI Power Challange System"
Bill Schmidt, SGI
The Packaging Technology for the IBM SP-2 Power Parallel Processor"
David Delia, IBM Kingston
"High Performance, Organic Single Chip Package"
William Petefish, W.L. Gore
12:00 to 1:00 PM LUNCH
"End of Workshop"
-----------Cut and print registration form from here-------
REGISTRATION
IEEE COMPUTER SOCIETY
TECHNICAL COMMITTEE ON COMPUTER AND SYSTEM PACKAGING
SPRING 1995 WORKSHOP
RANCHO MIRAGE, CALIFORNIA
(Please Return With Payment Before April 3, 1995)
NAME:
AFFILIATION:
MAILING ADDRESS:
PHONE:
FAX:
E-MAIL:
IEEE MEMBERSHIP NUMBER:
ALL WORKSHOP PARTICIPANTS MUST PRE-REGISTER
OPTIONS FEES (U.S. DOLLARS) TOTALS
[ ] *IEEE MEMBER REGISTRATION $25.00 $
[ ] *NON -- IEEE MEMBER REGISTRATION $35.00 $
[ ] *BASIC ROOM AND MEAL PLAN $530.00 $
[ ] **GUEST - MEAL PLAN & SHARE ROOM $189.00 $
GRAND TOTAL $
* Room and Meal Fee Includes All Meals, Receptions, and Refreshments,
From MONDAY Lunch, May 1 Through Lunch On Wednesday, May 3. All
Workshop Participants Must Pay the Basic Room/Meal Fee And the
Appropriate Registration Fee.
**A separate check may be used for the guest meal plan.
Cancellation Policy: No Refunds will Be Issued for Cancellations
Received After April 3, 1995.
HOTEL ARRANGEMENTS OUTSIDE BASIC WORKSHOP PACKAGE
[ ] April 30, 1995 (Saturday) $175 + TAX
[ ] April 31, 1995 (Sunday) $110 + TAX
[ ] May 3, 1995 (Wednesday) $110 + TAX
[ ] May 4, 1995 (Thursday) $110 + TAX
NOTE: The committee will make additional night hotel reservations,
however, attendees are responsible for payment directly to hotel for the
extra nights.
ENCLOSE CHECK OR CHECKS PAYABLE TO:
"IEEE COMPUTER SYSTEM PACKAGING COMMITTEE"
REMIT TO: FOR RESERVATIONS:
LEN ALTON, IEEE CSPC TREASURER RON KUNTZ
UNISYS CORP MAIL STOP 305 (619) 451- 4470
10850 VIA FRONTERA FAX (619) 451-5318
SAN DIEGO, CA. 92127 kuntz@PO1.rb.unisys.com
(619) 451-4556
FAX (619) 451-5318
alton@PO1.rb.unisys.com
Return to Conference Listing
Call for Papers
The Second International Conference on
MASSIVELY PARALLEL PROCESSING USING OPTICAL INTERCONNECTIONS (MPPOI)
October 23-24, 1995
San Antonio, Texas
Sponsored by:
ACM Special Interest Group on Architecture (SIGARCH)
The Optical Society of America (OSA)
Institute for Electrical and Electronic Engineers (IEEE - pending)
NSF - National Science Foundation (pending)
The second annual conference on Massively Parallel Processing
Architectures using Optical Interconnections (MPPOI'95) will be held on
Oct. 23-24, 1995 in San-Antonio, Texas. The Conference will focus on
the potential for using optical interconnections in massively parallel
processing systems, and their effect on system and algorithm design.
Optics offer many benefits for interconnecting large numbers of processing
elements, but may require us to rethink how we build parallel computer
systems and communication networks, and how we write applications. Fully
exploring the capabilities of optical interconnection networks requires an
interdisciplinary effort. It is critical that researchers in all areas of
the field are aware of each other's work and results. The intent of MPPOI is
to assemble the leading researchers and to build towards a synergetic
approach to MPP architectures, optical interconnections, operating systems,
and software development.
The topics of interest include but are not limited to the following:
Optical interconnections
Reconfigurable Architectures
Embedding and mapping of applications and algorithms
Packaging and layout of optical interconnections
Electro-optical, and opto-electronic components
Relative merits of optical technologies (free-space, fibers, wave
guides)
Passive optical elements
Algorithms and applications exploiting MPP-OI
Data distribution and partitioning
Characterizing parallel applications exploiting MPP-OI
Cost/performance studies
The conference will feature invited speakers, followed by several sessions of
submitted papers, and will conclude with a panel discussion.
Authors are invited to submit manuscripts which demonstrate original
unpublished research in areas of computer architecture and optical
interconnections. Papers submitted must not be under considerations for
another conference.
SUBMITTING PAPERS: All papers will be reviewed by at least 2 members of
the program committee. Send eight (8) copies of the complete paper
(not to exceed 15 single spaced, single sided pages) to:
============================================================================
DEADLINE: Papers must be sent so that they arrive on or before April 1, 1995
============================================================================
Dr. Eugen Schenfeld
MPPOI'95 Conference Chair
NEC Research Institute
4 Independence Way
Princeton, NJ 08540
USA
(voice) (609)951-2742
(fax) (609)951-2482
email: MPPOI@RESEARCH.NJ.NEC.COM
Manuscripts must be received by April 1st, 1995. Due to the
large number of anticipated submissions manuscripts arriving later than
the above date risk rejection. Notification of review decisions will
be mailed by July 1st, 1995. Camera ready papers are due
August 1st, 1995. Fax or electronic submissions will not be
considered. Proceedings will be published by the IEEE CS Press and will
be available at the symposium.
FOR MORE INFORMATION: Please write (email) to the Conference Chair.
Dr. Eugen Schenfeld
MPPOI'95 Conference Chair
NEC Research Institute
4 Independence Way
Princeton, NJ 08540
USA
(voice) (609)951-2742
(fax) (609)951-2482
email: MPPOI@RESEARCH.NJ.NEC.COM
PROGRAM COMMITTEE:
Karsten Decker, Swiss Scientific Computing Center, Manno, Switzerland
Jack Dennis, Lab. of CS, MIT, Boston, MA
Patrick Dowd, Dept. of ECE, SUNY at Buffalo, Buffalo, NY
Mary Eshaghian, Dept. of CS, NJIT, Newark, NJ
John Feo, Comp. Res. Grp., Lawrence Livermore Nat. Lab., Livermore, CA
Michael Flynn, Department of EE, Stanford University, Stanford, CA
Edward Frietman, Faculty of Applied Physics, Delft U., Delft, The Netherlands
Asher Friesem, Dept. of Electronics, Weizmann Inst., Israel
Kanad Ghose, Dept. of CS, SUNY at Binghamton, Binghamton NY
Allan Gottlieb, Dept. of CS, New-York University, New-York, NY
Joe Goodman, Department of EE, Stanford University, Stanford, CA
Alan Huang, Computer Systems Research Lab., Bell Labs., Holmdel, NJ
Yoshiki Ichioka, Dept. of Applied Physics, Osaka U., Osaka, Japan
Leah Jamieson, School of EE, Purdue University, West Lafayette, IN
Lennart Johnsson, Div. of Applied Science, Harvard U. and TMC, Cambridge, MA
Ahmed Louri, Dept. of ECE, U. of Arizona, Tucson, AZ
Kenichi Kasahara, Opto-Electronics Basic Res. Lab., NEC Corporation, Japan
Israel Koren, Dept. of ECS, U. of Mass, Amherst, MA
Raymond Kostuk, Dept. of ECE, U. of Arizona, Tucson, AZ
Philippe Lalanne, Inst. D'Optique, Orsay, France
Sing Lee, Dept. of EE, UCSD, La Jolla, CA
Steve Levitan, Department of EE, U. of Pittsburgh, Pittsburgh, PA
Adolf Lohmann, Institute of Physics, U. of Erlangen, Erlangen, Germany
Miroslaw Malek, Dept. of ECE, U. of Texas at Austin, Austin TX
Rami Melhem, Dept. of CS, University of Pittsburgh, Pittsburgh, PA
J. R. Moulic, IBM T. J. Watson Research Center, Yorktown Heights, NY
Miles Murdocca, Department of CS, Rutgers University, New Brunswick, NJ
John Neff, Opto-elec. Comp. Sys., U. of Colorado, Boulder, CO
Paul Prucnal, Department of EE, Princeton U., Princeton, NJ
Donna Quammen, Dept of CS, George Mason University, USA
John Reif, Department of CS, Duke University, Durham, NC
Anthonie Ruighaver, Dept. of CS, U. of Melbourne, Victoria, Australia
A. A. Sawchuk, Dept. of EE, USC, Los-Angeles, CA
Eugen Schenfeld, NEC Research Institute, Princeton, NJ
Pearl Wang, Dept. of CS, George Mason University, USA
Les Valiant, Div. of Applied Science, Harvard University, Cambridge, MA
Albert Zomaya, Dept. of EAEE, U. of Western Australia, Western Australia
===========================================================
Eugen Schenfeld
NEC Research Institute
4 Independence Way
Princeton, NJ 08540
phone: 609 951 2742
fax: 609 951 2482
email: eugen@research.nj.nec.com (Inet)
Andria Pierson Bader, Education Services
SPIE--The International Society for Optical Engineering
email: andria@spie.org
phone: 360/676-3290 ext. 655
fax:: 360/647-1445
Return to Conference Listing
Final Call for Participation
(Abstract Due Date: May 14th)
**********************
* THERMINIC Workshop *
**********************
International Workshop on Thermal investigations of ICs and Microstructures
September 25-26, 1995
Grenoble (Grand Hotel de Paris in Villard de Lans), France
(Submitted by: Bernard.Courtois@imag Bernard.Courtois@imag.fr)
The THERMINIC Workshop is the first of a series of events to discuss
the essential thermal questions of microelectronics and
microstructures. These questions are becoming more and more crucial
with the increasing element density of deep submicron downscaling of
integrated circuits necessitating thermal simulation, monitoring and
cooling. The high device density of MCMs and portable microsystems
raise new thermal problems to be solved in the near future. Thermal
effects, on the other hand, can be used as basis of sensor or other
functional structures. The Workshop intends to deal with all aspects
of thermal design, investigation and measurement of microcircuits and
microsystems.
The Workshop is co-sponsored by the BARMINT 8173 ESPRIT and the THERMINIC
00922 COPERNICUS Projects.
Committee :
General Chair Programme Chair
B. Courtois V. Szekely
TIMA Grenoble/France TU Budapest/Hungary
Vice General Chair
M. Rencz
TU Budapest/Hungary
Programme Committee
D. Esteve M. Glesner
LAAS-CNRS Toulouse/France TH Darmstadt/Germany
A. Napieralski W. Sansen
TU Lodz/Poland KU Leuven/Belgium
V. Koval C. Garres
TU Lvov/Ukraine Matra-Marconi Space Toulouse/France
E. Fourgeau M. Esashi
Zuken-Redac/France U. Tohoku/Japan
Y. Zorian G. De Mey
AT&T Bell Lab./USA U. Ghent/Belgium
J. Figueras C. Spencer
U. Barcelona/Spain IME/Singapore
G. Wrixon
NMRC Cork/Ireland
Areas of interest :
- Thermal Simulation
- Measuring and Monitoring of Thermal States
- Temperature Sensor Structures
- Smart Thermal Sensors
- Thermal problems of MEMs
- Thermal problems of microsystems
Vendor exhibition :
The THERMINIC Workshop invites vendors offering products in the scope
of the workshop to exhibit. Any company wishing to take part in the
exhibition should contact the general chair, preferably before the
31st of May, 1995, to be listed in the Programme booklet.
Information for the authors :
The Program Committee invites authors to submit papers describing
recent work. Panel proposals are also invited. Papers may be extended
summaries or full papers although preference will be given to full
paper submissions. In either case, clearly describe the nature of the
work, explain its significance, highlight novel features, and describe
its current status. On the title page, please indicate: title, name
and affiliations of all authors; an abstract of 50 words or less; and
topic outline. Also identify a contact author and include a complete
mailing address, phone number, fax number and E-mail address.
Speakers are not required to prepare full length papers for the workshop.
Submitted materials will be included in an informal Workshop Proceedings.
- Submission deadline (5 copies): 14 May 1995
- Notification of acceptance : 14 June 1995
- Submission of manuscripts for distribution at the Workshop
(optional) : 4 September 1995
Venue :
The location of the Workshop is the Grand Hotel de Paris in
Villard-de-Lans. The hotel is located in the heart of Villard-de-Lans,
in a 7.5 acres park. Grenoble can be reached by a three-hour train
ride from Paris, with 6 connections each day.
For further information, a copy of the Advance Program, or to
submit a paper or proposal, contact:
Bernard COURTOIS
TIMA
46 Avenue Felix Viallet Tel : (+33)76574615
38031 Grenoble cedex, France Fax : (+33)76473814
E-mail : Bernard.Courtois@imag.fr
Return to Conference Listing
BRASAGE 95: Soldering Technologies
Brest, France
September 20-22, 1995
(Submitted by: Laura Turbini laura.turbini@mse.gatech.edu)
Laura Turbini (404)853-9073
The International Conference on Soldering and Related Interconnection
Technologies will take place in Brest, France on September 20, 21 and 22,
1995. This conference addresses the changing demands on electronic
interconnections due to the miniaturization of discrete components,
chip-on-board, ball grid array and fine-pitch TAB packages which are
driving the evolution of fine line printed wiring substrates. The
evolving environmental constraints and the increasing requirement for
quality assurance to meet ISO 9000 Certification will also be
addressed.
This conference, know as BRASAGE '95 (Soldering '95) is organized by
the AFEIT (the association of companies affiliated with the
electronics, information and telecommunication industries in western
Brittany, France) and follows the International Conferences on
Soldering Fluxes and Paste held at Georgia Tech in Atlanta, Georgia in
1992 and 1994 and Brasage held in Lannion, France in 1993. A
committee of international experts has selected the speakers from
abstracts submitted on the following topics:
-- Influence of the environment and of circuit board components
on soldering technology choices
-- Substrate and Metallization
-- Fluxes and Pastes: low solids, no clean and water soluble
-- Alloys
-- Process Control
-- New Technologies
Presentations at the conference will be in English or French with
simultaneous translations and the Proceedings will contain papers in
either English or French. For more information on this conference,
please contact AFEIT at the following address:
AFEIT
BP 126
F-29268 BREST Cedex, FRANCE
Tel. (33)98 44 14 40
FAX (33)98 43 23 98
Or, to obtain the Advance Program and registration information, send
an email request (with your mailing address) to Prof. Laura J.
Turbini, Georgia Institute of Technology (at
laura.turbini@mse.gatech.edu).
This conference is sponsored by a number of French organizations and
by the IPC and Georgia Institute of Technology in the United States.
Return to Conference Listing
Twelfth Annual IEEE
SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM
Austin, Texas
March 1996
(Submitted by: Tom Tarter TOMT@MSD.AMD.COM
SEMI-THERM is an annual international forum for the presentation of
new developments in and applications relating to generation and
removal of heat within semiconductor devices, and measurement of
junction temperatures under various application and environmental
conditions. Attendance at the Symposium is limited, to preserve
the close interaction among attendees and presenters.
The Program Committee is now soliciting technical papers on current
thermal management and measurement work on electronic components and
systems in the following areas:
- Thermal Characterization
- Analytical and Computational Thermal Modeling
- Measurement Techniques Including Temperature, Fluid Flow, and
Thermal-Mechanical Properties
- Thermal Reliability Screening and Testing
Special focus will also be placed on papers emphasizing the
following topics:
- Low-Cost, High Performance Package Thermal Management
- Automotive Applications
- Passive Cooling Techniques
- Component and Board Level Thermal Management Innovations
Selection of papers for presentation is based only on the extended
abstract. Authors should submit a complete summary of the work
including key figures and tables. As a guide, 3-4 pages of single-spaced
text and an additional 2-3 figures would be usual. The abstract
must clearly state why the work is relevant to SEMI-THERM, what is
novel or unique about the work, it's significance, and the major
conclusions of the work. The abstract should also contain key results
supporting the conclusions and discuss the scope, organization, and
major points of the proposed paper. The proposed paper must consist
of work or results not previously presented or published. Submit your
abstract to the Program Chair by:
ABSTRACT DEADLINE: August 15, 1995
Submission of an abstract represents a commitment to submit a cleared
manuscript ready for publication in the Symposium Proceedings by December
15, 1995 and to attend and present the paper an SEMI-THERM in March of
1996.
Authors will be notified of paper acceptance by October 15, 1995.
Manuscripts are expected to be approximately eight pages including
figures. The language for the Symposium is English. IEEE membership
is not required to present a paper.
Send Abstracts To:
Program Chair:
Thomas S. Tarter
Advanced Micro Devices
P.O. Box 3453, Mail Stop 58
Sunnyvale, CA 94088-3453
Phone: (408)982-6468
Fax: (408)982-6164
email: tomt@msd.amd.com
Return to Conference Listing
FIRST ANNOUNCEMENT & CALL FOR PAPERS
EUROTHERM Seminar No. 45,
"THERMAL MANAGEMENT OF ELECTRONIC SYSTEMS"
September 20-22, 1995, Leuven, Belgium
Hosted by IMEC
SCOPE OF THE SEMINAR
The EUROTHERM Seminar No. 45 is the 2nd one on the subject of Thermal
Management of Electronic Systems. Eurotherm Seminar no. 29 has proven that a
lot of European electronics industries and research institutes are involved
with thermal management aspects.
During the last decade, thermal engineering has won increasing importance in
the design of electronic equipment. Reducing the lead time in the design and
manufacturing of electronic equipment requires a concurrent engineering
approach. Miniaturisation, increasing heat fluxes and increasing reliability
demands continues to drive the need for more efficient thermal management
techniques both at the component and system levels. User-friendly software
tools have been developed in order to predict the flow and temperature fields
in electronic systems. One major issue is the temperature dependence on the
overall reliability of an electronic system.
This EUROTHERM Seminar will be a forum for exploring progress in the analysis
of heat transfer and thermally induced failures in electronic systems. The
Seminar will highlight the role of mechanical engineering in an integrated
design approach using existing E-CAD and M-CAD software tools.
TOPICS OF THE SEMINAR
The Program Committee is soliciting contributed papers on the following
topics:
Thermal characterisation
Characterisation of packages, heat-sinks, and systems
Contact resistance in electronic equipment
Transient thermal characterisation
Single and multi-phase convective cooling
Natural and forced convection air and liquid cooling
Heat transfer in small enclosures
Jet impingement cooling
Application of heat pipes
Measurement techniques
Flow visualisation techniques
Fluid velocity and temperature measurement techniques
Measurement techniques in operational Systems
Measurement of thermo-mechanical properties
Analytical and computational thermal modelling
Computational fluid dynamics modelling
Turbulence modelling in electronic equipment
Radiation heat transfer
Thermo-mechanical modelling
Electro-thermal modelling
Integrated simulation tools
Thermal reliability
Temperature dependent reliability models
Thermally induced stresses
Thermal fatigue
SCIENTIFIC PROGRAMME
The seminar programme will consist of invited papers, contributed papers and
poster presentations. An exhibition of relevant software- and hardware tools
will be included. Two pre-conference tutorials will be separately organised.
REGISTRATION AND FEES
Information requests, registration forms and paper submissions should be
addressed to the conference secretary:
Mrs. C. Deboes, IMEC, Kapeldreef 75, B-3001 Heverlee BELGIUM,
Phone ++32 16 28 12 81, Fax ++32 16 28 15 01
The registration fee for the three-day seminar will be about 10000 Bef and
includes the proceedings, lunches, coffee and a seminar dinner.
VENUE
The Seminar will be hosted by IMEC in Leuven. Leuven is located about 20 km
east of Brussels and the international airport.
CALL FOR PAPERS
Experts in industry, university and research institutes are invited to submit
a 500-word abstract including key figures. Paper selection is based on the
abstract only. It must clearly describe the purpose, results, significance
and conclusions of the proposed work. Five copies of the abstract should be
sent to the conference secretary.
Submission of a paper represents a commitment to either attend the seminar or
send a knowledgeable substitute who can answer questions regarding the
reported work.
LANGUAGE OF THE SEMINAR
The official language for the seminar and its publications is English.
DEADLINES
* Abstracts must be submitted to the seminar chairman by April 14, 1995.
* Authors will be notified of paper acceptance, with full instructions for
publication by May 8, 1995.
* Final date for receipt of manuscripts: July 7, 1995.
ORGANISING COMMITTEE
Dr. ir. E. Beyne (Chairman), IMEC, Leuven, Belgium
Ir. C.J.M. Lasance (Co-chairman), Philips CFT, Eindhoven, The Netherlands
Prof. J. Berghmans (Program Chairman), Katholieke Universiteit Leuven,
Belgium
SCIENTIFIC COMMITTEE
Prof. J.P. Bardon, Universiti de Nantes, France
Prof. G. Cesini, Universita di Ancona, Italy
Dr. R.Dumcke, Technische Universitat Berlin, Germany
Prof. C. Hoogendoorn, J.M. Burgers Centre, Univ. of Delft, The Netherlands
Prof. A.Van Steenhoven, Technische Universiteit Eindhoven, The Netherlands
Dr. C. O Mathuna, Power Electronics Ireland
Prof. G. De Mey, Universiteit Gent, Belgium
Prof. J. Saulnier, Lab. de Thermique, ENSMA, Poitiers, France
Dr. D. Tatchell, Flomerics, London, United Kingdom
U.S. Liaison: : Prof. A. Ortega, University of Arizona, Tucson AZ
ABOUT EUROTHERM
The EUROTHERM Committee was created in 1986 from member countries of the
European Community. It has the purpose of organising and coordinating
scientific events such as seminars and conferences in the thermal sciences.
The series of EUROTHERM Seminars established by the Committee has become a
popular forum for high-level scientific and technical interchange of ideas in a
wide range of specialist topics. The primary aim is to stimulate discussion
and liaison between specialist groups. The chairman of EUROTHERM is Professor
K. Stephan of the Stuttgart University (fax ++ 49 711 685 6140). Information
of future Seminars is available from the Secretary, Professor D.Gorenflo,
University (GH) Paderborn (fax ++ 49 5251 60 3522).
Return to Conference Listing
Plastic Encapsulated Microelectronics: Materials,
Processes, Tests, Reliability, and Applications; edited by M.
Pecht, L. Nguyen, and E. Hakim.
The past twenty years have seen many important advances in
plastic encapsulated microcircuit (PEM) technology. Thanks to
new packaging materials, improved design and manufacturing
processes, and other important developments, PEMs are now a
dependable and cost-effective option for a wide range of
electronic systems applications. Nevertheless, there continue to
be challenges to the design and use of PEMs.
For the first time, there is a comprehensive, critical
review of the state of the art in PEMs and the assemblies that
incorporate them. The most timely book on the subject, it
provides professionals with a systematic, scientific exploration
of all crucial technology and reliability issues concerning the
manufacture and use of PEMs, with special attention to
environment-specific applications. Among the important topics
covered in detail are:
- Encapsulating materials -- composition, properties and
characteristics;
- Fabrication technology -- with an in-depth look at potential
defects that can occur during assembly
- Failure mechanisms -- sites and modes;
- Failure analysis techniques -- relative strengths and
weaknesses;
- Screening techniques -- the pros and cons of using these
technique for reliability conformance and quality
improvement and their correlative defects; and
- Qualification and life testing techniques -- their
effectiveness in simulating use conditions.
This book is published by John Wiley & Sons and can be
purchased by contacting them at 605 Third Avenue, New York, NY
20158-0012, or (212) 850-6000.
*** ***
Carl A. Rust, Executive Director E-mail: rust@eng.umd.edu
CALCE Electronic Packaging Research Center Phone: (301) 405-5323
Room 1103, Engineering Laboratory Building FAX: (301) 314-9269
University of Maryland
College Park, MD 20742
Return to Conference Listing
Plastic Encapsulated Microelectronics
Materials, Processes, Tests, Reliability, and Applications
An Intensive Short Course for Engineers and Managers
CALCE Electronic Packaging Research Center
University of Maryland
March 15-16, 1995
BACKGROUND
The use of best commercial practice microcircuits offers
advantages of cost, reliability, size, weight, and availability,
over the traditional, military approved microcircuits. The
traditional barrier to the use of these commercial parts has been
perceptions of lower reliability in military and commercial
aerospace applications. However, the avionic and military
industries have begun to reconsider the use of commercial parts
due to 1) improvements in reliability of best commercial practice
microcircuits resulting from improved materials and process
control; 2) a heightened level of skepticism about the
traditional probabilistic reliability prediction methods; 3)
improved methods of reliability assessment using physics-of-
failure; 4) awareness that factors other than "part reliability"
are more important than previously thought; 5) concerns that some
military part numbers may not be available throughout the life of
product/system under development; and 6) relentless cost
pressures which can be eased by the use of best commercial
practice parts.
Implementation of these commercial parts in high reliability
military and commercial applications requires the ability to
evaluate their capabilities in specific designs and operating
environments; an understanding of their interaction with
manufacturing and assembly processes; the capability to evaluate
and predict their impact on reliability; and a system to specify,
procure, and control their use.
This course is the collection of results of many years of
work by leading edge researchers. The purpose of the course is
to use sound scientific principles to present practical, hands-on
ways to evaluate and use best commercial practice microcircuits
in real applications. It is a how-to course for the use and
assessment of commercial microcircuits in a variety of
applications.
The course is intended for electronic equipment
manufacturers, parts manufacturers, and their government and
industrial customers. The information presented will be of
benefit to executives, managers, design and manufacturing
engineers, procurement, and marketing personnel.
COURSE OUTLINE
The two-day course is divided into six sessions, each of
which presents a different aspect of this timely subject. Each
subject is presented at a practical level, and each principle is
illustrated with examples.
Session 1. The New World of High Reliability and Usage
An overview of the historical development of plastic-encapsulated
microcircuits, which shows how the traditional
military/industrial approach to their use is being modified in
response to technical innovation and the changing economic and
political scene. This technology is presented in comparison with
hermetic packaging technology, along with a comparison of their
strengths and weaknesses (both technical and economic).
Session 2. Plastic Parts Technology
A summary of the materials which compose plastic-encapsulated
microcircuits and the key design steps and manufacturing
processes.
Session 3. Physics of Failure Concept and Models
Actual plastic package decapping is demonstrated and key failure
sites are shown and discussed. Methods to assess the reliability
of components using physics of failure models are presented,
along with methods to improve processes.
Session 4. Handling and PWB Assembly Issues
A description of the manufacturing of electronic systems using
plastic encapsulated components. Particular attention is paid to
the processes that can affect the reliability of PEMs on circuit
cards. Aspects of shipping containers and handling that are of
special significance during storage, transportation, and pre-
assembly including information pertaining to moisture and
electrostatic discharge protection in containers are discussed.
Session 5. Accelerated Testing and Screening
An overview of the various types of accelerated tests and ESS
methods, is presented. This session shows how and when to use
each type of test, and how to evaluate and eliminate unnecessary
testing and screening. Methods to relate performance under one
set of conditions to reliability under other conditions are
discussed.
Session 6. Managing Commercial Component Use
A comprehensive, pro-active system for specifying, procuring, and
managing the use of commercial parts in both design and
manufacturing is essential for success. This session covers areas
that must be addressed by such a system, and shows how to avoid
the many potential pitfalls in the change from military to
commercial technologies.
PRESENTERS
Dr. Michael Pecht is a Professor and the Director of the CALCE
Electronic Packaging Research Center at the University of
Maryland. He has a M.S. in Electrical Engineering and a M.S. and
Ph.D. in Engineering Mechanics from the University of Wisconsin.
He is a Professional Engineer, an IEEE Fellow, and a former
Westinghouse Professor. He serves on the board of advisors for
various companies. He is the chief editor of the IEEE
Transactions on Reliability, and a section editor for the Society
of Automotive Engineering.
Edward B. Hakim is Chief of the Component Reliability Branch,
Army Research Laboratory, Fort Monmouth, New Jersey. Mr. Hakim
has a M.S. in Physics from the University of Connecticut. He has
been involved in Army microelectronic and semiconductor
reliability R&D since 1962. Prior to Fort Monmouth, he was with
IBM in Poughkeepsie, New York. He has authored and presented
over 60 technical papers on various semiconductor reliability
topics and has authored the book entitled, Microelectronic
Reliability, Volume I: Reliability, Test, and Diagnostics,
published by Artech House.
Dr. Mary Li is Director of the Electronic Packaging Failure
Analysis Laboratory at the University of Maryland. She has a
Ph.D. in Materials Science and is an expert in conducting
research on failure mechanisms of plastic encapsulated
microcircuits.
Leon Lantz II is a senior chemist at the DoD where he is program
manager for development of novel surface coating to provide
environmental protection of ICs. He has an M.S. in Chemistry, is
a member of the RWoH consortium and consults on various
government programs associated with plastic packaging development
and test approaches.
REGISTRATION INFORMATION
The registration fee of $695 includes all costs of instruction,
text, handouts, parking, lunch and refreshment breaks. For a
registration form and further information, please contact:
Joan Lee
CALCE Electronic Packaging Research Center
University of Maryland
College Park, MD 20742
Phone: (301) 405-5323
Fax: (301) 314-9269
*** ***
Carl A. Rust, Executive Director E-mail: rust@eng.umd.edu
CALCE Electronic Packaging Research Center Phone: (301) 405-5323
Room 1103, Engineering Laboratory Building FAX: (301) 314-9269
University of Maryland
College Park, MD 20742
Return to Conference Listing
ANNOUNCEMENT
International Symposium on Printed Wiring Board Technology
- A View from Japan - (Mini-Exhibition & Presentations)
April 18-21, 1995
HKPC Building, Yau Yat Chuen, Kowloon, Hong Kong
Organizer: Hong Kong Productivity Council
Keynote Speakers:
Kiyoshi Takagi, Takagi Associates
Naoharu Horino, Oki Electric Industry Co., Ltd.
Masamitsu Aoki, Toshiba Chemical Corporation
Toshiki Sasabe, Digital Equipment Corporation Japan
Tadashi Kobayashi, Kobayashi PC Technology Office
Keynote Papers:
1-1 Technology Trends of Manufacturing Processes (Takagi)
o Required characteristics for multilayer printed wiring boards
o Classification of multilayer printed wiring boards and their
manufacturing processes
o Issues on multilayer printed wiring board manufacturing
o Application to the multichip module substrate
1-2 Layout Design and Computer Automated Design of Printed Circuit
Board (Horino)
o Transfer from a maximum space utilization to an optimized
electric characteristics
o CAD and CAE technologies to support the board design
o Thermal management for board design
2-1 Copper Clad Laminates for Surface Mount Technology (Aoki)
o Market Trend
o Electronics Appliance Trend
o New Applications of CCL Material
2-2 Topics on Manufacturing Process Control (Sasabe)
o Pattern Plating or Panel Plating?
o Plating Defects: its causes and cures.
o Qualification programs and ISO9000
3-1 Inspection, Testing and Reliability Assessment (Kobayashi)
o Inspection Technology for High-Density PWB -- Technology
trend of continuity testers and automatic optical inspection
o Reliability of High-Density PWB -- Thin Boards, Small vias,
Pad on vias, surface finishes and others
3-2 Group Discussion with Questions and Answers (Roundtable
Discussion)
Enquiries to:
Mr. Daniel Chan
Hong Kong Productivity Council
Phone: +852-788-5738 FAX: +852-788-5770
or email to:
sasabe@tbjlab.enet.dec.com
(Mr Toshiki Sasabe, Digital Equipment Corporation)
Return to Conference Listing
CAll FOR PAPERS
IEEE Multi-Chip Module Conference
MCMC-96
Tutorials: February 5, 1996
Conference: February 6-7, 1996
The Cocoanut Grove, Santa Cruz, CA
Sponsored by:
------------
Circuits and Systems Society
Computer Society
Components, Packaging & Manufacturing Technology Society
Electron Devices Society
Steering Committee:
------------------
Chair
David B. Tuckerman, nCHIP, Inc.
Technical Program
Paul D. Franzon, North Carolina State University
Local Arrangements
Lisa Pascal, University of California, Santa Cruz
Tutorials
Rui Wang, Intel Corporation
Exhibits
Wayne W. Dai, University of Calirornia, Santa Cruz
Past Chair
Robert C. Frye, AT&T Bell Labortories
Asia Liaison
Yuji Okuto, NEC Corp., Japan
Europe Liaison
Bernard Courtois, TIMA/CMP, France
Sung-Mo (Steve) Kang, University of Illinois
James D. Murphy, ARPA
David W. Palmer, Sandia National Labs
King L. Tai, AT&T Bell Laboratories
Jan Vardaman, TechSearch International
Simon Wong, Stanford University
Conference Highlights:
---------------------
Tutorials: In-depth presentation covering relevant MCM related topics.
Technical Sessions: Single track designed to foster interaction among
chip designers, system designers, CAD tool developers, and MCM
technologists.
Invited Talks: Address the latest developments and future trends.
Panel Discussions: Interactive discussions of immediate needs, problem
areas, concerns and innovative solutions.
Exhibits: MCM foundry, Known Good Die technology, MCM design tools,
simulation and layout benchmark posters.
Technical Papers Are Solicited On, But Not Limited To:
-----------------------------------------------------
Design For MCM: system and chip design specifically targeted for MCM
technology -- custom I/O buffers, packaging-driven partition, design
for test, design for manufacturability, design for cost.
MCM Technology for low power systems: minimum capacitance design,
portable electronics.
Analysis: modeling and simulation of electrical and thermal behavior of
MCM structures, noise analysis, delay analysis, performance and cost
driven design.
Applications: innovative uses of MCM technology, system-level optimization.
Technology: novel MCM structures and fabrication methods, integral passive
and active elements, high-frequency and optical interfaces.
Testing: methodology, design and technology for MCM test, Known Good Die,
die- and wafer-level burn-in, boundary scan and built-in self-test
applied to MCMs.
Infrastructure: standards, MCM foundry, university and small company access
to MCM technology.
SUBMISSION DEADLINE: August 12, 1995
Authors should submit an extended abstract (not exceeding 2000 words, plus
figures). The extended abstract should contain sufficient details to permit
a careful review for technical excellence. Authors should clearly state
their contribution and point out new and significant results. Submissions
may be made by mail, fax, or e-mail.
All appropriate company and government clearances must be obtained prior
to submission.
Please send extended abstract to:
Paul D. Franzon
Electrical & Computer Engineering
North Carolina State University
Raleigh, NC 27695-7911
TEL 919-515-7351
FAX 919-515-5523
paulf@ncsu.edu
For advance program and other information:
MCMC-96
Attn: Lisa Pascal
Computer Engineering, University of California
Santa Cruz, CA 95064
TEL 408-459-2263
FAX 408-459-4829
lisa@cse.ucsc.edu
Notice of acceptance will be mailed by September 20, 1995. Authors of
accepted papers will be expected to provide a camera ready manuscript of
up to 6 pages on IEEE supplied model paper by November 15, 1995, for
publication in the conference proceedings.