Volume 2, Number 3
April 24, 1995
- CALENDAR OF CONFERENCES/MEETINGS
- EUROTHERM Seminar No. 45 (ECTC)
September 20-22, 1995. Leuven, Belgium
- THERMINIC Workshop
September 25-26 , 1995. Grand Hotel de Paris in Villard de Lans, Grenoble,
France
- 4th IEEE Multi-Chip Module Conference
Spring 1996 Workshop
February 5-7, 1996. The Cocoanut Grove, Santa Cruz, CA.
- 4th Topical Meeting on Electrical Performance of Electronic
Packaging (EPEP '95)
October 2-4, 1995. Portland, Oregon
- VHDL-Forum for CAD in Europe
April 24 - 27, 1995. NANTES, France.
- ESPRIT Project 8370-ESIP Workshop
April 24 - 27, 1995. NANTES, France.
- Workshop on Design Methodologies for Microelectronics
September 11 - 13, 1995. Smolenice Castle, Slovakia; Vienna, Austria.
- Meeting on Pan-European Co-operation and Technology Transfer
September 11 - 13, 1995. Smolenice Castle, Slovakia; Vienna, Austria.
- X Congress of the Brazilian Microelectronics Society
July 31 to August 4,1995. Canela, BRAZIL.
- I Ibero-American Microelectronics Conference
July 31 to August 4,1995. Canela, BRAZIL.
- Adhesives in Electronics '96
Second International Conference on Adhesive Joining and Coating Technology in
Electronics Manufacturing, June 3-5 1996. Stockholm, Sweden
- Workshop on Interconnections within High Speed Digital Systems
May 14-15, 1995. Sante Fe, New Mexico
- SHORT COURSES
- OTHER CONFERENCES OF INTEREST
- RECENT BOOKS
- POSITIONS OPEN
CONFERENCES AND WORKSHOPS
FIRST ANNOUNCEMENT & CALL FOR PAPERS
Eurotherm '95
EUROTHERM Seminar No. 45
Leuven, Belgium
September 20-22, 1995
Hosted by IMEC
Submitted by: Eric Beyne
a1::beyne"%mrgate@imec.be
SCOPE OF THE SEMINAR
The EUROTHERM Seminar No. 45 is the 2nd one on the subject of Thermal
Management of Electronic Systems. Eurotherm Seminar no. 29 has proven that a
lot of European electronics industries and research institutes are involved
with thermal management aspects.
During the last decade, thermal engineering has won increasing importance in
the design of electronic equipment. Reducing the lead time in the design and
manufacturing of electronic equipment requires a concurrent engineering
approach. Miniaturisation, increasing heat fluxes and increasing reliability
demands continues to drive the need for more efficient thermal management
techniques both at the component and system levels. User-friendly software
tools have been developed in order to predict the flow and temperature
fields in electronic systems. One major issue is the temperature dependence
on the overall reliability of an electronic system.
This EUROTHERM Seminar will be a forum for exploring progress in the
analysis of heat transfer and thermally induced failures in electronic
systems. The Seminar will highlight the role of mechanical engineering in an
integrated design approach using existing E-CAD and M-CAD software tools.
TOPICS OF THE SEMINAR
The Program Committee is soliciting contributed papers on the following
topics:
Thermal characterisation
Characterisation of packages, heat-sinks, and systems
Contact resistance in electronic equipment
Transient thermal characterisation
Single and multi-phase convective cooling
Natural and forced convection air and liquid cooling
Heat transfer in small enclosures
Jet impingement cooling
Application of heat pipes
Measurement techniques
Flow visualisation techniques
Fluid velocity and temperature measurement techniques
Measurement techniques in operational Systems
Measurement of thermo-mechanical properties
Analytical and computational thermal modelling
Computational fluid dynamics modelling
Turbulence modelling in electronic equipment
Radiation heat transfer
Thermo-mechanical modelling
Electro-thermal modelling
Integrated simulation tools
Thermal reliability
Temperature dependent reliability models
Thermally induced stresses
Thermal fatigue
SCIENTIFIC PROGRAMME
The seminar programme will consist of invited papers, contributed papers and
poster presentations. An exhibition of relevant software- and hardware tools
will be included. Two pre-conference tutorials will be separately organised.
REGISTRATION AND FEES
Information requests, registration forms and paper submissions should be
addressed to the conference secretary:
Mrs. C. Deboes, IMEC, Kapeldreef 75, B-3001 Heverlee BELGIUM,
Phone ++32 16 28 12 81, Fax ++32 16 28 15 01
The registration fee for the three-day seminar will be about 10000 Bef and
includes the proceedings, lunches, coffee and a seminar dinner.
VENUE
The Seminar will be hosted by IMEC in Leuven. Leuven is located about 20 km
east of Brussels and the international airport.
CALL FOR PAPERS
Experts in industry, university and research institutes are invited to
submit a 500-word abstract including key figures. Paper selection is based
on the abstract only. It must clearly describe the purpose, results,
significance and conclusions of the proposed work. Five copies of the
abstract should be sent to the conference secretary.
Submission of a paper represents a commitment to either attend the seminar
or send a knowledgeable substitute who can answer questions regarding the
reported work.
LANGUAGE OF THE SEMINAR
The official language for the seminar and its publications is English.
DEADLINES
* Abstracts must be submitted to the seminar chairman by April 14, 1995.
* Authors will be notified of paper acceptance, with full instructions for
publication by May 8, 1995.
* Final date for receipt of manuscripts: July 7, 1995.
ORGANISING COMMITTEE
Dr. ir. E. Beyne (Chairman), IMEC, Leuven, Belgium
Ir. C.J.M. Lasance (Co-chairman), Philips CFT, Eindhoven, The Netherlands
Prof. J. Berghmans (Program Chairman), Katholieke Universiteit Leuven,
Belgium
SCIENTIFIC COMMITTEE
Prof. J.P. Bardon, Universiti de Nantes, France
Prof. G. Cesini, Universita di Ancona, Italy
Dr. R.Dumcke, Technische Universitat Berlin, Germany
Prof. C. Hoogendoorn, J.M. Burgers Centre, Univ. of Delft, The Netherlands
Prof. A.Van Steenhoven, Technische Universiteit Eindhoven, The Netherlands
Dr. C. O Mathuna, Power Electronics Ireland
Prof. G. De Mey, Universiteit Gent, Belgium
Prof. J. Saulnier, Lab. de Thermique, ENSMA, Poitiers, France
Dr. D. Tatchell, Flomerics, London, United Kingdom
U.S. Liaison: : Prof. A. Ortega, University of Arizona, Tucson AZ
ABOUT EUROTHERM
The EUROTHERM Committee was created in 1986 from member countries of the
European Community. It has the purpose of organising and coordinating
scientific events such as seminars and conferences in the thermal sciences.
The series of EUROTHERM Seminars established by the Committee has become a
popular forum for high-level scientific and technical interchange of ideas
in a wide range of specialist topics. The primary aim is to stimulate
discussion and liaison between specialist groups. The chairman of EUROTHERM
is Professor K. Stephan of the Stuttgart University (fax ++ 49 711 685
6140). Information of future Seminars is available from the Secretary,
Professor D.Gorenflo, University (GH) Paderborn (fax ++ 49 5251 60 3522).
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Final Call for Participation
THERMINIC Workshop
September 25-26 , 1995
Grenoble, France
(Grand Hotel de Paris in Villard de Lans)
September 25-26 , 1995
Submitted by: Bernard Courtoise
Bernard.Courtois@imag.fr
The THERMINIC WWorkshop is the "International Workshop on Thermal
investigations of ICs and Microstructures". The THERMINIC Workshop is the
first issue of a series of events to discuss the essential thermal questions
of microelectronics and microstructures. These questions are becoming more
and more crucial with the increasing element density of deep submicron
downscaling of integrated circuits necessitating thermal simulation,
monitoring and cooling. The high element density of MCMs and the mobile
parts of microsystems raise newer and newer thermal problems to be solved in
the near future. Thermal effects on the other hand can be used as bases of
sensor or other functional structures. The Workshop intends to deal with all
aspects of thermal design, investigation and measurement of microcircuits and
microsytems.
The Workshop is co-sponsored by the BARMINT 8173 ESPRIT and the THERMINIC
00922 COPERNICUS Projects.
Committee :
General Chair Programme Chair
B. Courtois V. Szekely
TIMA Grenoble/France TU Budapest/Hungary
Vice General Chair
M. Rencz
TU Budapest/Hungary
Programme Committee
D. Esteve M. Glesner
LAAS-CNRS Toulouse/France TH Darmstadt/Germany
A. Napieralski W. Sansen
TU Lodz/Poland KU Leuven/Belgium
V. Koval C. Garres
TU Lvov/Ukraine Matra-Marconi Space Toulouse/France
E. Fourgeau M. Esashi
Zuken-Redac/France U. Tohoku/Japan
Y. Zorian G. De Mey
AT&T Bell Lab./USA U. Ghent/Belgium
J. Figueras C. Spencer
U. Barcelona/Spain IME/Singapore
G. Wrixon
NMRC Cork/Ireland
Areas of interest :
- Thermal Simulation
- Measuring and Monitoring of Thermal States
- Temperature Sensor Structures
- Smart Thermal Sensors
- Thermal problems of MEMs
- Thermal problems of microsystems
Vendor exhibition :
The THERMINIC Workshop invites vendors offering products in the scope of
the workshop to exhibit.
Any company wishing to take part in the exhibition should contact the
general chair, preferably before the 31st of May, 1995, to be listed in the
Programme booklet.
Information for the authors :
The Program Committee invites authors to submit papers describing recent
work. Panel proposals are also invited. Papers may be extended summaries or
full papers although preference will be given to full paper submissions. In
either case, clearly describe the nature of the work, explain its
significance, highlight novel features, and describe its current status.
On the title page, please indicate : title, name and affiliations of all
authors, an abstract of 50 words or less, and suggested topics. Also
identify a contact author and include a complete mailing address, phone
number, fax number and E-mail address.
Speakers are not required to prepare full length papers for the workshop.
Submitted materials will be included in an informal Workshop Proceedings.
- Submission deadline (5 copies): 14 May 1995
- Notification of acceptance : 14 June 1995
- Submission of manuscripts for distribution at the Workshop (optional) :
4 September 1995
Venue :
The location of the Workshop is the Grand Hotel de Paris in
Villard-de-Lans. The hotel is located in the heart of Villard-de-Lans, in a
7,5 acres park. A tennis court and practice for golf are available in the
park (18 hole golf at Correncon en Vercors at 5 kilometers).
Villard-de-Lans is located in the Vercors, a national park and well
preserved site in a varied setting, that only a medium altitude mountain
area can offer : forests, flowers, combs, caves, gorges. Hundreds of
kilometres of well-marked foot-paths for rambling, riding or biking, a real
paradise for climbers, speleologists, canyoning, not forgetting paragliding
and hot-air balloons.
Grenoble can be reached via the following links :
by car : 3 highways from north, east, west,
by train : 6 TGV connections per day - (Paris - Grenoble 2 hours 58
minutes),
by plane : via the airports of Grenoble-St Geoirs, Lyon-Satolas or
Geneve-Cointrin. There are shuttles to get to Grenoble.
A special bus will take the participants from/to Grenoble to/from
Villard-de-Lans.
Submit all paper proposals and/or intentions to participate to :
Bernard COURTOIS
TIMA
46 Avenue Felix Viallet
38031 Grenoble cedex, France
E-mail : Bernard.Courtois@imag.fr
Bernard COURTOIS TIMA - CMP Tel : (+33)76574615
E_mail Bernard.Courtois@imag.fr Telex : INPG 320 205 F
46 avenue Felix Viallet Fax : (+33)76473814
38031 GRENOBLE CEDEX - FRANCE
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Call For Program and Announcement
IEEE Multi-Chip Module Conference
The Cocoanut Grove, Santa Cruz, CA
Tutorials: February 5, 1996
Conference: February 6-7, 1996
Submitted by:
Dave Palmer (David_W._Palmer@smtplink.mdl.sandia.gov)
and
David Tuckerman (davidt@nchip.com)
Sponsored by:
Circuits and Systems Society
Computer Society
Components, Packaging & Manufacturing Technology Society Electron
Devices Society
Steering Committee:
Chair
David B. Tuckerman, nCHIP, Inc.
Technical Program
Paul D. Franzon, North Carolina State University
Local Arrangements
Lisa Pascal, University of California, Santa Cruz
Tutorials
Rui Wang, Intel Corporation
Exhibits
Wayne W. Dai, University of Calirornia, Santa Cruz
Past Chair
Robert C. Frye, AT&T Bell Labortories
Asia Liaison
Yuji Okuto, NEC Corp., Japan
Europe Liaison
Bernard Courtois, TIMA/CMP, France
Sung-Mo (Steve) Kang, University of Illinois
James D. Murphy, ARPA
David W. Palmer, Sandia National Labs
King L. Tai, AT&T Bell Laboratories
Jan Vardaman, TechSearch International
Simon Wong, Stanford University
Conference Highlights:
Tutorials: In-depth presentation covering relevant MCM related
topics.
Technical Sessions: Single track designed to foster interaction among
chip designers, system designers, CAD tool developers, and MCM
technologists.
Invited Talks: Address the latest developments and future trends.
Panel Discussions: Interactive discussions of immediate needs,
problem areas, concerns and innovative solutions.
Exhibits: MCM foundry, Known Good Die technology, MCM design tools,
simulation and layout benchmark posters.
Technical Papers Are Solicited On, But Not Limited To:
* Design For MCM: system and chip design specifically targeted for MCM
technology -- custom I/O buffers, packaging-driven partition, design
for test, design for manufacturability, design for cost.
* MCM Technology for low power systems: minimum capacitance design,
portable electronics.
* Analysis: modeling and simulation of electrical and thermal behavior
of MCM structures, noise analysis, delay analysis, performance and cost
driven design.
* Applications: innovative uses of MCM technology, system-level
optimization.
* Technology: novel MCM structures and fabrication methods, integral
passive and active elements, high-frequency and optical interfaces.
* Testing: methodology, design and technology for MCM test, Known Good
Die, die- and wafer-level burn-in, boundary scan and built-in self-test
applied to MCMs.
* Infrastructure: standards, MCM foundry, university and small company
access to MCM technology.
SUBMISSION DEADLINE: August 12, 1995
Authors should submit an extended abstract (not exceeding 2000 words,
plus figures). The extended abstract should contain sufficient
details to permit a careful review for technical excellence. Authors
should clearly state their contribution and point out new and
significant results. Submissions may be made by mail, fax, or e-mail.
All appropriate company and government clearances must be obtained
prior to submission.
Please send extended abstract to:
Paul D. Franzon
Electrical & Computer Engineering
North Carolina State University
Raleigh, NC 27695-7911
TEL 919-515-7351
FAX 919-515-5523
paulf@ncsu.edu
Notice of acceptance will be mailed by September 20, 1995. Authors of
accepted papers will be expected to provide a camera ready manuscript
of up to 6 pages on IEEE supplied model paper by November 15, 1995,
for publication in the conference proceedings.
For advance program and other information:
MCMC-96
Attn: Lisa Pascal
Computer Engineering, University of California Santa Cruz, CA 95064
TEL 408-459-2263
FAX 408-459-4829
lisa@cse.ucsc.edu
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ANNOUNCEMENT AND CALL FOR PAPERS
4TH TOPICAL MEETING ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING
(EPEP '95)
Portland, Oregon
October 2-4, 1995
Submitted by: Paul Franzon
paulf@eos.ncsu.edu
and
Alina Deutsch
deutsch@watson.ibm.com
Sponsored by :
The IEEE Microwave Theory and Techniques Society
The IEEE Components, Packaging and Manufacturing Technology Society
C0-Chairs:
A. Deutsch, IBM Corporation
V.K. Tripathi, Oregon State University
The general subject of the meeting is the electrical design, analysis,
and characterization of electronic interconnections and packaging for
performance-driven, high speed/high complexity electronic systems. A
forum will be provided for the discussion of the following topics as they
relate to chip-to-chip and on-chip interconnections in electronic systems:
* Package analysis, including numerical methods and algorithms;
electro-magnetic analysis tools; advances in transmission-line
techniques.
* New and innovative interconnect and packaging structures and
their electrical performance.
* RF/Microwave packaging structures and their electrical performance.
* MMIC modules and high density packaging.
* Experimental Characterization techniques and testing procedures.
* EMC/EMI effects; prediction and measurement of radiation from
inter-connect structures and packaged systems.
* Electrical requirements, limits of performance.
* Novel designs, design methods, wire placement and routing systems.
* Low cost, high volume packaging
* Optoelectronic packaging; structure and system applications.
* Packaging concerns for wireless communication;design and modelling.
* Current and future issues related to on-chip interconnections;
performance limits.
PAPER SUBMISSION
Authors are invited to submit papers describing new technical
contributions in the areas broadly covered above. The original and three
copies of a summary, not to exceed three pages, including illustrations,
are required for paper selection. All papers must be written in
English. The title of the paper and the names and affiliations of all
the authors including complete mailing address, telephone , FAX number
and e-mail, must appear on the first page of the summary, as well as a
35-word abstract. FAX and e-mail are absolutely necessary since all
paper acceptance notifications and further communications will be done
via one of these media. If the paper is accepted, the summary will
be reproduced, as is, in the meeting's digest. AN IEEE TRANSFER OF
COPYRIGHT, FOUND IN MOST IEEE JOURNALS, MUST ACCOMPANY EACH SUBMISSION.
Submission should be sent, no later than June 7, 1995, to the address below.
Several half and full-day SHORT COURSES will be offered on Sunday,
October 1 in conjunction with the topical meeting. Proposals for these
courses must be submitted to the co-chairs by April 28, 1995.
PRODUCT DISPLAYS
Parties interested in displaying products and software packages at this
meeting should contact the address below.
-------------------------------------------------------------------------
___ I am interested in the Electrical Performance of Electronic Packaging
Meeting.
___ I plan to submit an abstract and summary by June 7, 1995.
___ I am interested in attending the short courses.
___ Please send Preliminary Program
NAME______________________________________________________________
COMPANY/AFFILIATION_______________________________________________
MAILING ADDRESS___________________________________________________
CITY______________________________________________________________
STATE_________ZIP__________________COUNTRY________________________
TELEPHONE_________________________FAX_____________________________
E-MAIL____________________________________________________________
Please return to:
EPEP'95
Engineering Professional Development
University of Arizona
Box 9, Harvill Building, Room 235
Second and Olive Streets
Tucson, Arizona 85721-0076
(520) 621-3054/5104
FAX: (520) 621-1443
E-Mail: baltes@bigdog.engr.arizona.edu
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Program & Invitation
VHDL-FORUM for CAD in EUROPE
Spring '95 Working Conference
and
ESPRIT Project 8370-ESIP
WORKSHOP ON LIBRARIES,
COMPONENT MODELING,
AND QUALITY ASSURANCE
IRESTE - IHT, NANTES, France
April 24 - 27, 1995
Submitted by Adam Pawlak
Adam.Pawlak@imag.fr
Main Sponsor: SIG-VHDL, IFIP WG 10.5/ECSI
Co-Sponsors: ATLANTECH, IRESTE, TEMIC/MATRA MHS
General Information
Location: IRESTE (Institut de Recherche et d'Enseignement Superieur
aux Techniques de l'Electronique)
IHT (Institut des Hommes et de la Technologie)
Nantes, France
Dates: Tutorial Sessions* VHDL-Forum Europe
April 24, 1995 General Sessions
(morning) April 24-25, 1995
CAE Exhibition Workshop on Libraries, Component
April 25-26, 1995 Modeling, and Quality Assurance
April 26-27, 1995
VHDL-Forum for CAD in Europe
Spring '95 Working Conference
IRESTE, NANTES, France
The VHDL-Forum for CAD in Europe (VFE) is the European users'
group active in VHDL-related topics & standardization efforts
and was founded at the International Federation for Information
Processing (IFIP) conference VLSI '89 in Munich by IFIP WG 10.5.
Since the founding of the IFIP/ECSI Special Interest Group on
VHDL (SIG-VHDL) in spring '94 the VFE is supported by this
group. The VFE members belong to an international range of companies,
institutes, and universities. The VFE is open to all interested participants.
The motivation and history of the group was the diverse European experiences in
the field of hardware description languages and related topics.
During the first two years, the main emphases of the VFE were
the promotion and education of VHDL in Europe and the establishment
of relationships to international VHDL users' groups (USA, Japan)
and standardization groups. The VFE and the EuroVHDL conferences,
as complementary, more research-oriented events, have built the
European VHDL network with international connections.
Both events, the EuroVHDL and the VFE, are going to be coordinated
and organized under the umbrella of SIG-VHDL.
The Spring '95 working conference focuses on user-oriented topics,
because more and more European users are in the migration phase
towards VHDL and have collected experiences in practise.
Exchange of design experience is required, although the link between
research and industrial application of VHDL is an important issue
as well. Additionally, accompanying standards and standardized
practises around VHDL have emerged during the previous year(s).
VHDL-based tools, graphical entry, simulator backplane, cycle-based
simulator, animator, standard modeling techniques for sign-off
descriptions, synthesis with link to layout, hardware/software
co-design promise better solutions for the users. What are the
real benefits? These are topics to be addressed at the Spring '95
working conference.
VFE-Board:
D. Borrione, France, A. Hohl, Germany, J. Mermet, France,
G. Musgrave, U.K., W. Nebel, Germany, S. Olcoz, Spain,
F. Rammig, Germany, E. Villar, Spain.
Program Committee:
P. Bakowski, IRESTE, France, A. Balboni, Italtel, Italy,
D. Borrione, Artemis/IMAG, France, J.P. Caisso, Matra-MHS, France,
N. Dutt, University of California, USA, H. Hegny, Bosch Telecom ANT,
Germany, A. Hohl, Siemens, Germany, S. Krolikoski, Compass Design
Automation, USA, S. Maerz-Roessel, Siemens, Germany, J. Mermet, ECSI
Office, Artemis, France, P. Miller, University of Portsmouth, U.K.,
G. Musgrave, Brunel University, U.K., W. Nebel, University of Oldenburg,
Germany, S. Olcoz, TGI, Spain, A. Pawlak, Artemis/IMAG, France,
P. Prinetto, Politecnico di Torino, Italy, F. Rammig, University of
Paderborn, Germany, D. Sciuto, Politecnico di Milano, Italy, E. Villar,
University of Cantabria, Spain.
Local Organization:
F. Bouchard, J. P. Caisso, J. F. Diouris, G. Ramstein
Program Chairperson:
Przemyslaw Bakowski, IRESTE/SEI, University of Nantes, France
Conference Secretary:
IRESTE, La Chantrerie, CP 3003, 44087 Nantes cedex 03, France
Phone: 33-40.68.30.79 Fax: 33-40.68.30.66
e-mail: pbakowsk@ireste.fr
Monday, April 24, 1995
8.00-14.00 Registration
9.00 Tutorial Sessions
* Introduction to ASIC Cells Modeling With VITAL
O. Levia, Synopsys, USA
* Introduction to VHDL 1993 and Shared Variables
Stanley J. Krolikoski, COMPASS Design Automation, USA
* VHDL and Associated Methods
Jean-Michel Berge, France Telecom-CNET, France
* Synthesis applications of VHDL
Eugenio Villar, Microelectronics Group of the University of
Cantabria, Spain
* Formal Methods for Hardware Verification: Overview and Application to
VHDL,
Carlos Delgado Kloos and Peter T. Breuer, Universidad Politecnica
de Madrid (UPM), Spain
14.00 Opening Session
Opening Remarks: P. Bakowski
Welcoming: B. Remaud, Y. Thomas, A. Dantec, J. Mermet, W. Nebel
Keynote Address: Ron Waxman
"The Union of Specification Modeling with the Design Process."
The talk will address the motivation for integrating specification
modeling into the design process, how it may be accomplished, and
the benefits derived from the process.
15.30 Coffee Break
16.00 Specification and System Design
Session Chair: C. Delgado Kloos, Univ. Politecnica de Madrid, Spain
* System Performance Modeling and Analysis with VHDL: Benefits and
Limitations,
J-P. Calvez, D. Heller, O. Pasquier, IRESTE, France
* Modeling Shared Variables in VHDL - a Pragmatic Approach
J. Wytrebowicz, Institut National des Telecommunications, France
* An Environment for Electronic Systems Simulation based on VHDL
G. Lehmann, M. Wolff, B. Wunder, K. D. Mueller-Glaser, Univ.
Karlsruhe, Germany
17.30-19.00 Vendors presentation
Tuesday, April 25, 1995
9.00 Synthesis
Session Chair: F. Rammig, Univ. Paderborn/CadLab
* Validating Subroutines of the VHDL Synthesis Packages
W. Ecker, Siemens AG, Germany
* Resource Constrained VHDL Synthesis from Algorithmic Description
K. Djigande, S. Crand, P. Bakowski, J-F. Diouris, D. Jeuland,
IRESTE, France
* VHDL Synthesis Description Portability: The Need for Level-x
Synthesis Subsets
E. Villar, ETSI Industriales y de Telecomunicacion, Spain,
W. Ecker, Siemens AG, M. Selz, Univ. Erlangen-Nurnberg, Germany
10.30 Coffee Break
11.00 FPGA Modeling and Synthesis
Session Chair: E. Villar, Univ. Cantabria, Spain
* Experiences with VHDL and FPGAs
L. Lindh, J. Furunas, J. Starner, Malardalens Univ., Sweden
* VHDL-based Rapid Hardware Prototyping Using FPGA Technology
M. Khosravipour, H. Gruenbacher, Vienna Univ. of Technology, Austria
12.00 Break
13.00 Lunch
14.30 Test
Session Chair: J-P. Caisso, MATRA MHS, France
* Assessment of Functional Testability Properties from VHDL Descriptions
C. Bolchini, Politecnico di Milano, M. Bombana, Italtel SIT,
G. Buonanno, Politecnico di Milano, P. Cavalloro, Italtel SIT,
F. Ferrandi, D. Sciuto, Politecnico di Milano, G. Zaza, Italtel SIT,
Italy
* An Approach to Checking the Completeness of Stimuli (short paper)
T. Gabler, Siemens AG, Germany
* A Complete Test Methodology for Validating ASIC Workstation Libraries
(short paper)
Ph. Leclair, J-F. Rousseleau, MATRA MHS, France
15.40 Coffee Break
16.00 Tools
Session Chair: A. Balboni, Italtel SIT, Italy
* Specific Image Processing Designed with an Original VHDL Front-End Tool
O. Deforges, G. Ramstein, P. Bakowski, IRESTE, France
* Unified ASIC Library Development Suite
R. Bedi, P. Deshmukh, Viewlogic Systems, USA
17.00 Panel: Does Synthesis Need Simulation ?
Panel Chair: S. Krolikoski, Compass DA, USA
19.30 Conference Dinner
Boat trip on the river Erdre
10.00-18.00 Exhibition
Wednesday April 26, 1995
9.00-16.00 Exhibition
ESPRIT Project 8370-ESIP
Workshop on Libraries, Component Modeling, and Quality Assurance
in cooperation with IFIP WG 10.5 and ECSI
System designers need libraries of component models. Current
libraries of models are in most cases neither portable nor
compatible. This is caused by the lack of generally accepted
rules for the development of models. The VITAL initiative is a
big step towards changing this scenario for ASIC models. High
model development costs for complex components and difficulty to
protect proprietary rights of model developers constitute further
obstacles.
The objective of this workshop is to gather engineers developing
models and responsible for libraries of components, designers
using models in a board-level simulation, vendors developing tools,
and academic people to discuss the state-of-the-art problems and
solutions related to building libraries of sign-off, accurate,
fast, portable, compatible and correct models of digital, analogue
and mixed components.
9.00 Opening
9.15 Models of Complex Components
Session chair: D. Borrione, ARTEMIS/IMAG, France
* Model Availability, Portability and Accuracy -
An IC Vendor's Perspective, Efforts and Vision for the Future
W. Hobbs, Intel Corporation, USA
* Prototyping: the Bottom Line of VHDL System Simulation
S. Olcoz, L. Entrena, L. Berrojo, J. Goicolea, TGI, Spain
* Aspects of Modeling a Library of Complex and Highly Flexible
Components in VHDL
V. Preis, Corporate Research and Development, Siemens AG, Germany
10.45 Coffee break
11.15 Model Generation Tools
Session chair: R. Waxman, Univ. of Virginia, USA
* An Expert Assistant for Hardware Systems Specifications
L. Chaouat, Ch. Munk, A. Vachoux, D. Mlynek, EPFL-DE-LEG/C3i,
Switzerland
* MELODY: An Efficient Layout-Based Models Generator
F. Delguste, F. Igier, F. Lepine, MATRA-MHS, France
* Implementing VITAL: The COMPASS Model Generator
S. Krolikoski, M. Grossman, Compass Design Automation, USA
12.45-14.30 Lunch
14.30 Quality Concepts
Session chair: %%To be decided%%
* Modern Concepts of Quality and Their Relations to Model Libraries
L. Jozwiak, Eindhoven Univ. of Technology, The Netherlands
* Quality Measures and Analysis: a way to improve VHDL models
M. Mastretti, ITALTEL SIT, M. Sturlesi, S. Tomasello, Univ. degli Studi
di Milano, Italy
15.30 Coffee break
16.00 Industrial Requirements and Modelling Standards
Session chair: M. Laurent, MATRA MHS, France
* Standards for Interoperability and Portability
S. Hurat, Thomson-CSF/SCTF, France
* The Usage of VHDL in the European Space Agency
P. Sinander, ESA/ESTEC, The Netherlands
17.00 Short coffee break
17.15-18.15 Experiments with Analog HDLs
Session chair: J-M. Berge, France Telecom-CNET, France
* Analog and Mixed Modeling with HDL-A - An Evaluation
F. Lemery, J.P. Morin, E. Nercessian, SGS-THOMSON Microelectronics,
France
* Modelling and Simulation of Microsystems - An Experience with HDL-A
B. Romanowicz, Ph. Lerch, Ph. Renaud, Inst. de Microtechnique,
A. Vachoux, Centre de Conception de Circuits Integres, Switzerland
Thursday, 27 April 1995
9.00 VITAL Modelling
Session chair: Oz Levia, Synopsys, USA
* Issues in Efficient Modeling and Acceleration of VITAL Modules
S. Nayak, A. Roy, CADENCE Design Systems, India
* Fault Modelling in VITAL
J.L. Barreda, P. Sanchez, E. Villar, Univ. of Cantabria, Spain
10.00 Short coffee break
10.15 Status of VITAL standardization
Session chair: Victor Berman, Chair IEEE DASC WG on VHDL Timing
Methodology, USA
- Status for IEEE standardization and short term objectives
- Longer term objectives with discussion
- Implications for sign-off
- In-depth discussion of changes to 2.2b and some detailed examples
of complex cell designs
11.45 Discussion Workshop
Session chair: Adam Pawlak, ARTEMIS/IMAG, France
This discussion session will focus on two topics: a database format
for library information exchange, which can be used among others to
generate ASIC libraries and store data for timing calculation, and
the next VITAL-like effort required to stimulate further growth of
VHDL.
* ALEX - A Database Tool to Automate the Support of Multiple ASIC
Library Format
R. Bedi, ViewLogic, USA
* The Next VHDL Time Bomb
S. J. Krolikoski, Chair VHDL International Technical Activity Committee
13.00 Closing of the Workshop
General Chair: General Vice-Chair: Program Chair:
Adam Pawlak Sylvie Hurat Dominique Borrione
ARTEMIS/IMAG Thomson-CSF/SCTF ARTEMIS/IMAG
Grenoble, France Orsay, France Grenoble, France
Demonstration Chair: Local Arrangements:
Jean-Michel Berge Przemyslaw Bakowski
France-Telecom CNET, Meylan, France IRESTE/Univ. of Nantes, France
Program Committee:
E. Abel, GMD, Germany, J. Armstrong, Virginia Tech, USA,
P. Bakowski, IRESTE/Univ. of Nantes, France, A. Balboni,
Italtel, Italy, J-M. Berge, France-Telecom CNET, France,
V. Berman, Cadence, USA, D. Borrione, ARTEMIS/IMAG, France,
N. Dutt, Univ. of California Irvine, USA, H. Gruenbacher,
TU Vienna, Austria, S. Hurat, Thomson-CSF/SCTF, France,
M. Laurent, Matra MHS, France, O. Levia, Synopsys, USA,
S. Krolikoski, Compass DA, USA, P. Menchini, Menchini & Ass,
USA, J. Mermet, ECSI and Univ. Fourier, France, G. Moretti,
Intergraph Electronics, USA, Z. Navabi, Univ. Tehran, Iran,
W. Nebel, Univ. Oldenburg, Germany, S. Olcoz, TGI, Spain,
A. Pawlak, ARTEMIS/IMAG, France, F. Rammig, Univ. of Paderborn,
Germany, J. Rouillard, ESIM, France, S. Schulz, TI, USA,
E. Schutz, Alcatel Mietec, Belgium, R. Stewart, SGS-Thomson,
France, A. Vachoux, EPFL, Switzerland, E. Villar, Univ. of
Cantabria, Spain, R. Waxman, Univ. of Virginia, USA, R. Werner,
Motorola, USA, T. Yamaguchi, NEC Corp., Japan, A. Zamfirescu,
Intergraph Electronics, USA
CAE Exhibition accompanying VHDL-Forum and the Workshop
Location: The exhibition will take place in the central "street" of IRESTE.
Opening Hours:
Tuesday, 25 April 1995 from 10:00 till 18:00
Wednesday, 26 April 1995 from 9:00 till 16:00
The exhibition is open to all registered participants of VHDL-Forum
and of the Workshop.
Exhibitors:
Leading CAE tool vendors have been invited to present their latest
products.
Contact Person:
Jean-Paul Caisso tel: (33) 40 18 18 75
MATRA MHS fax: (33) 40 18 18 00
Route de Gachet e-mail: jean-paul.caisso@matramhs.fr
CP 3008
F-44087 NANTES cedex 03
A copy of the progam as well as useful information
is available on WWW at http://www.ireste.fr,
choose "Les seminaires et colloques organises a l'IRESTE"
REGISTRATION FORM
VHDL-Forum for CAD in Europe, Spring '95 Working Conference and
Workshop on Libraries, Component Modeling, and Quality Assurance
April 24 - 27, 1995, Nantes, France
There is one common registration procedure for both VHDL-Forum
and the Workshop. By registering to the event, a participant is
entitled to take part in VHDL-Forum and the Workshop, and to visit
the exhibition. He will receive both volumes of proceedings.
(In order to confirm your registration, this form should be
returned before March 25, 1995)
Last Name: .....................................................
First Name: .....................................................
Affiliation: .....................................................
Address: .....................................................
City: .....................................................
ZIP Code: .....................................................
Country: .....................................................
Phone/Fax: .....................................................
Membership No.(*): .................................................
Tutorials: (Limited number of attendees, book in time. Please tick one)
1. Tutorial: Introduction to ASIC Cells Modeling With VITAL ...
2. Tutorial: Introduction to VHDL 1993 and Shared Variables ...
3. Tutorial: VHDL and Associated Methods ...
4. Tutorial: Synthesis applications of VHDL ...
5. Tutorial: Formal Methods for Hardware Verification:
Overview and Application to VHDL ...
VHDL-Forum and Workshop Received before Received after
Registration Fees: March 25, 1995 March 25, 1995
or On-Site
Member ECSI, IFIP or
affiliated Organization(*) 1900 FF 2100 FF
Non-member 2000 FF 2200 FF
Student (enclose a copy of
your Univ. ID-card) 400 FF 500 FF
Tutorials:
(The fee is for one tutorial) 600 FF 700 FF
Payment: (Please tick fees above and choose the tutorial you want
to attend.)
... Payment by personal cheque drawn on a French Bank or international
cheque (Traveller's cheque, EuroCheque, etc) in French Francs payable
to IRESTE-A.
... Payment by International Bank Transfer in French Francs to
account No. 0000022421Z, key 54 at bank No. 30047, desk 00019
(C.I.O. Carquefou). A copy of the remittance slip must be attached
to the registration form. It must clearly state 'VHDL Forum' and
the participant's name and company.
... Payment on-site by cheque (see conditions on the first method
of payment) or by international credit card: VISA, EUROCARD, or
MASTERCARD.
Date: .................
Signature:
After completing all sections, mail this form to:
Frederique Bouchard, VHDL-Forum Spring'95, IRESTE, La Chantrerie, CP 3003,
F-44087 Nantes cedex 03, France
Phones: 33-40.68.30.49, 33-40.68.30.79 Fax: 33-40.68.30.66
e-mail: fbouchar@ireste.fr
(*) IEEE, ACM, IEE, BCS, SEE, AFCET
The above registration fee includes -except for students- admission
to all technical sessions of VHDL-Forum and the Workshop, to the
exhibition, the banquet, morning and afternoon refreshments, lunches,
and a copy of the proceedings of VHDL-Forum and the Workshop. For
students, the banquet, the lunches and the copies of the proceedings
are not included.
CANCELLATION. No refunds will be made unless a written request for
cancellation received prior to March 25, 1995. All refunds are subject
to a 10% processing fee. Substitutions will be accepted at any stay.
HOTEL RESERVATION FORM
VHDL-FORUM for CAD in EUROPE, Spring'95
and Workshop on Libraries, Component Modeling, and Quality Assurance
NANTES, APRIL 24-27, 1995
IMPORTANT: Mail completed form directly to the chosen hotel.
Last Name ..........................................................
First Name .........................................................
Affiliation .......................................................
Mailing Address ....................................................
Country ............................................................
Phone Number ......................................................
Fax Number .........................................................
Please reserve: ... a single room ... a double room for .... nights
Expected date and time of arrival: .................................
Departure date: ....................................................
SPECIAL RATES HAVE BEEN NEGOTIATED IN THE HOTELS LISTED BELOW
(Price given breakfast included)
*** Hotel de Bourgogne
9, allee du Cdt Charcot, F-44000 Nantes
Ph : (33) 40.74.03.34
Fax: (33) 40.14.03.86
Single Room: 290 FF
Double Room: 310 FF
330 FF (2 Twin beds)
*** Hotel de Vendee
8, allee du Cdt Charcot, F-44000 Nantes
Ph : (33) 40.74.14.54
Fax: (33) 40.74.77.68
Single Room: 300 FF
Double Room: 320 FF
*** Hotel de France
24, rue Crebillon, F-44000 Nantes
Ph : (33) 40.73.57.91
Fax: (33) 40.69.75.75
Single Room: From 350 FF
Double Room: From 392 FF
*** Hotel Le Jules Verne
Square Fleuriot de l'Angle, F-44000 Nantes
Ph : (33) 40.35.74.50
Fax : (33) 40.20.09.35
Single Room: From 339 FF
*** Hotel La Perouse
3 Allee Duquesne, F-44000 Nantes
Ph : (33) 40.89.75.00
Fax: (33) 40.89.76.00
Single Room: From 390 FF
*** Hotel Adagio
4, rue de Couedic, F-44000 Nantes
Ph : (33) 51.82.10.00
Fax: (33) 51.82.10.10
Single Room: 605 FF
Double Room: 670 FF
A deposit covering the charge for one night must be enclosed. It will
be deducted from the hotel bill. If no deposit is enclosed, requests
for hotel reservation will not be guaranteed.
Should you wish to cancel your reservation, please do so by mail,
fax or telegram at least 2 weeks prior to the anticipated date of
arrival. Otherwise, the hotel will retain your deposit and no refund
will be made.
Hotel reservations will be handled on a first come first served basis.
It is therefore in your interest to mail your hotel reservation form
together with your deposit as soon as possible.
All prices are given in French Francs so kindly make your payment in
that currency.
_______________________
Return to Index
Return to Conference Listing
CALL for contributions for EAST-WEST co-operation build-up event
Workshop on DESIGN METHODOLOGIES FOR MICROELECRONICS
Smolenice Castle, Slovakia
Vienna, Austria
September 11 - 13, 1995
and
Two special days on PAN-EUROPEAN CO-OPERATION AND TECHNOLOGY TRANSFER.
Smolenice Castle, Slovakia
Vienna, Austria
September 14, 15 1995
Submitted by: Adam.Pawlak@imag.fr
This event is the first major forum of the BENEFIT Concerted Action launched
recently by the European Commission in a frame of the COPERNICUS programme.
This forum comprises:
* a workshop on DESIGN METHODOLOGIES FOR MICROELECRONICS
and
* two SPECIAL DAYS on PAN-EUROPEAN CO-OPERATION AND TECHNOLOGY TRANSFER.
Different kinds of contributions are solicited: regular papers for the
workshop and reports for the Special Days programme.
Adam Pawlak
General Chair
pawlak@imag.fr
IMAG/ARTEMIS
----------------------------------------------------------------
Workshop: September 11-13, 1995, Smolenice castle
----------------------------------------------------------------
The AIM OF THE WORKSHOP is to present and discuss research results
in the areas of design methodologies in microelectronics and their
applications, support and accelerate a pan-European exchange of ideas,
confront research directions undertaken by its participants,
additionally stimulated by lectures given by invited experts, identify
challenging problems providing possibilities for a fruitful
collaboration, and discover potential partners for common projects.
Workshop topics:
* Electronic Systems Modelling
* Architectures for High Performance Signal Processing
* Field Programmable Logic
* Neural Networks
* Artificial Intelligence Techniques
* Hardware/Software Co-Design
* Design for Testability
* Mixed D/A Design
* Performance Driven Synthesis
* Applications:
- DSP
- Telecommunications
- Biomedicine and Biocybernetics
- etc.
Paper Submission
Monday, April 3, is the deadline for paper submission.
The complete papers (up to 8 pages) or extended
abstracts (min. 500 words), in English, are to be sent
(e-mail strongly recommended) to the Programme Committee Chairman,
Prof. Michal Servit:
Czech Technical University
Karlovo Namesti 13
CZ - 121 35 Praha
Czech Republik
Tel. +42 2 2435 7473
Fax +42 2 298 098
E-mail Servit@cslab.felk.cvut.cz
----------------------------------------------------------------
Special Day on Co-operation: September 14, 1995, Smolenice castle
----------------------------------------------------------------
Chair: Manfred Horvat, Bureau for International Research and
Technology Co-operation B.I.T., Vienna
Co-chair: Marco Cecchini, CEC, DGIII - Industry, Brussels
This special session will give a concise introduction into the RTD
Programmes of the European Community: their underlying principles,
objectives and contents, as well as their operational characteristics.
A special focus will be put on methodological and technical issues
essential for European collaborative research: preparation of proposals,
setting up a project consortium managerial approaches, methods and tools
for transnational research projects. In addition, presentation of case
studies by experienced project co-ordinators from different programmes
will provide an insight into the real life of this challenging
development of research in Europe.
Contributions monitoring experience of collaborative projects run
under ESPRIT, EUROCHIP, TEMPUS, COPERNICUS and other European programmes
pointing to obstacles but also to possibilities and chances for better,
more efficient co-operation are especially welcomed. Please submit your
report (up to 8 pages, in English) before May 1, 1995 to:
Manfred Horvat
B.I.T.
Wiedner Hauptstr. 76 phone: +43-1-581 16 16-114
A-1040 Vienna fax: +43-1-581 16 16-16
Austria e-mail: horvat@bit.ac.at
----------------------------------------------------------------------
Vienna Industrial Day: September 15, 1995, Vienna
----------------------------------------------------------------------
Chair: Kurt Judmann, Technical University of Vienna
The objective of the industrial day is to provide a forum for CEE
researchers as well as West European companies to present resources,
results and demands in the field of scientific and technical
collaboration.
CEE researchers are invited to present their work and resources. West
European companies are invited to present reports on current projects.
Prospective presenters are asked to submit a report clearly describing
the essential elements of their achievements including: field
of application, critical estimation of market chances, and own
capacities for collaboration. Further, access to communication means
and language capabilities should be mentioned.
Submissions (up to 8 pages, in English) should be addressed to
the Industrial Day Chair before May 1, 1995:
Kurt Judmann
Institut fur Computertechnik 384
TU-Vienna
Gusshausstrasse 27-29 phone: +43 1 505 37 83
A-1040 Vienna fax: +43 1 505 73 42
Austria e-mail: judmann@ict.tuwien.ac.at
The deadline for paper submissions for both Special Days (i.e.
Special Day on Co-operation and Industrial Day) is Monday, May 1st.
More information on the BENEFIT Concerted Action may be obtained from:
Dr. Roland Pleger
DLR, Project Management Division
Linder Hoehe
D-51147 Cologne
email: roland.pleger@dlr.de
and from
Dr. Tadeusz Grabowiecki
Instutute of Electronics
Silesian Technical University
Pl-44-101 Gliwice
e-mail: tgrab@boss.iele.gliwice.edu.pl
Address of LOCAL ORGANIZERS:
Institute of Computer Systems, Slovak Academy of Sciences
Faculty of Electrical Engineering, Slovak Technical University
Milan Duda
Institute of Computer Systems
Dubravska cesta 9 phone: +42 7 371 008
842 37 Bratislava fax: +42 7 371 004
Slovakia e-mail: DMM-95@savba.savba.sk
SMOLENICE CASTLE
The Smolenice castle, surrounded by beautiful park, is towering
above the village of Smolenice at the eastern foothill of Mali
Karpaty (Small Carpatians), about 60 km far from Bratislava.
The castle was originally preceded by a stronghold watching the Czech Road,
and it was destroyed and abandoned in late 18th century. From this medieval
stronghold only a part of the outside rampart with cannon bastion is
preserved. Renovation of the castle in Romantic style, started in late 19th
century, was finished in 1955. Now the castle is owned by the Slovak Academy
of Sciences and is used to shelter both recreation and work (conferences,
seminars, etc.).
---------------------------------------------------------------------
PRELIMINARY REGISTRATION FORM
Workshop on Design Methodologies for Microelectronics
and Special Days on pan-European Co-operation and Technology Transfer
Name and title:
Institution:
Address:
Country:
Telephone:
Fax:
E-mail:
I plan to submit a paper for the Workshop: yes no
I plan to submit a paper for the Special Day on Co-operation: yes no
I plan to submit a paper for the Vienna Industrial Day: yes no
Please give a title of your prospective contribution
.....................................................
I plan to attend the Industrial Day in Vienna: yes no
The registration fee will be approx. US$ 145. The registration
fee includes proceedings, local transportation (Bratislava -
Smolenice and back; Bratislava - Vienna and back) and all-day
meals during the Workshop and the Special Day in Smolenice
including the invitation dinner.
I plan to apply for a grant: yes no
Preliminary accommodation reservation
Date of arrival:
Date of departure:
Accommodation will be provided at the historical Smolenice
castle and Dolna Krupa mansion in either single-, double- or
three-bed rooms, at the price US$ 26 - 35 per person and day.
Please return this form by mail, e-mail or fax to:
DMM-95 Secretariat
Institute of Computer Systems
Dubravska cesta 9 phone: +42 7 371 008
842 37 Bratislava fax: +42 7 371 004
Slovakia e-mail: DMM-95@savba.savba.sk
Return to Index
Return to Conference Listing
FINAL CALL FOR PAPERS
X SBMICRO
I IBERMICRO
X Congress of the Brazilian Microelectronics Society
I Ibero-American Microelectronics Conference
Canela, BRAZIL
July 31 to August 4,1995
Organized by: BRAZILIAN MICROELECTRONICS SOCIETY - SBMICRO
FEDERAL UNIVERSITY OF RIO DE GRANDE DO SUL - UFRGS
Submitted by: Ricardo Reis
Ricardo Reis
Instituto de Informatica - Universidade Federal do Rio Grande do Sul
Av. Bento Goncalves, 9500 - Campus do Vale - Bloco IV
C.P.15064 , CEP 91501-970 Porto Alegre BRASIL
Tel: +55-51- 2281633 / Ext. 6830 or 3368399 / Ext. 6830
Fax: +55-51- 3365576 Fax Alternative: +55-51-3362779 or 2272295
E_Mail: Reis@inf.ufrgs.br
THE CONFERENCE:
The annual congress of the Brazilian Microelectronics Society brings
together specialists and researchers in several areas related to
microelectronics. In its tenth edition, SBMICRO will take place
jointly with the 1st Ibero-American Microelectronics Conference.
The strenghtening of the cooperation and technical exchange among
Latin-American and Iberian specialists is sought by this joint
event, which tries to consolidate and expand the interaction within
Latin America.
The following activities will take place in the days of the Conferences:
technical sessions, invited papers, tutorial courses, technical panels,
exhibition of university projects and industrial products.
CONFERENCE LOCATION:
SBMICRO and IBERMICRO will be held in the mountains of the
Brazilian southern state of Rio Grande do Sul, in the tourist town of Canela,
near Porto Alegre. Canela and Gramado (6km from canela) are known by the
influence of German immigration in the region. With its Bavarian
architectural style, Canela is surrounded by beautifull mountains and
provides an excellent environment for conferences or meetings.
AREAS OF INTEREST:
Authors from all around the world are invited to submit original papers in
all areas of microelectronics. Topics include, but are not limited to:
. Analog and Digital IC Design
. CAD for VLSI Design
. Simulation, Verification, and Testing
. High Level Synthesis
. Fabrication Processes
. Materials, Devices and Circuits
. Instrumentation for Microelectronics
. Embedded Systems
. Architecture and Algorithms
. Microelectronics education
General Chair: Sergio Bampi / UFRGS, Brazil
Technical Program Chair: Ricardo Reis / UFRGS, Brazil
SUBMISSION OF PAPERS:
Contributions will be accepted in English only: papers
up to 10 pages long, for oral presentation in technical sessions. Camera-ready
originals plus 3 (three) copies should be sent to the address below, where
additional information can be obtained.
PANELS, TUTORIALS AND ROUND-TABLES
Suggestions for the conference activities around Panels, Tutorials and
Round-Table discussions can be submitted to the Conference Chairmen until
December 30, 1994, stating topics, abstract, and list of potential panelists
and invited participants.
Secretaria Eventos - Instituto de Informatica -UFRGS
Caixa Postal 15064 CEP 91501-970 Porto Alegre - RS - Brazil
Telephone: + 55-51-3368399 or 2281633 ext: 6830 Fax: +55-51-3365576
E-Mail: eventos@inf.ufrgs.br
IMPORTANT DEADLINES:
Submission of manuscripts: April 14th, 1995 (postage)
Notifications of acceptance: May 31st, 1995
PAPER FORMAT:
The papers have to be submitted in camera-ready format, in A4 paper
(297x210mm), leaving 25mm margins on each side. The first page should
include the title, author(s) identification, author(s) affiliation, and
abstract. Pages should not be numbered in the original text.
Return to Index
Return to Conference Listing
Call for Papers
ADHESIVES IN ELECTRONICS '96
Second International Conference on
Adhesive Joining and Coating Technology in
Electronics Manufacturing
June 3-5 1996
Stockholm, Sweden
Following the successful First International Conference on Adhesives in
Berlin on November 3-5 1994 we are now happy to announce the Second
International Conference to be held in Stockholm on June 3-5 1996. Polymeric
electronic packaging using adhesives in electronics manufacturing will be a
key technology in future electronics. The conference is designed for
researchers, users, and suppliers to meet and share their knowledge and
experience. Both oral and poster presentations are solicited.
Call for papers
Please send an abstract in English of less than 300 words no later than
December 23, 1995. The abstract should clearly describe the nature, scope,
key points, and significance of the paper. The abstract should also present
the experimental methodology and significant results achieved. Papers
selection will be made by February 29, 1996, with final camera ready
manuscripts, of accepted abstracts due by April 19, 1996.
Abstracts and all other correspondence should be sent to the conference office.
Technical topics
-Adhesives and coatings (for example optical, electrical and thermal)
-Design, Simulation, Modelling
-Reliability and life cycle analysis
-Processing and application techniques
-Packaging and interconnecting technology (including flip-chip, optical
interconnection, MCM, DCA, surface mounting, BGA, TAB, COB, through-hole
mounting)
-Materials, including isotropic and anisotropic conducting adhesives,
heat-seal connectors, thermo-setting and thermo-plastic systems,
UV-curable adhesives
-Environmental issues, ecological and eco-toxicological aspects
-Other novel technologies
Exhibition
Suppliers of materials, equipment, test and analysis instruments,
universities and research institutes are invited to present new products and
research results. There will be a fee of SEK 6000 for an exhibition stand.
Conference office
Sveriges Verkstads Industrier
VI-The Association of Swedish Engineering Industries
Storgatan 5
P.O. Box 55 10
S-11485 STOCKHOLM
Sweden
Tel: +46 8 782 0959
Fax: +46 8 782 0864
Attn: Asa Midbeck
Organizing and Program Committee
Anders Marcelius VI, Sweden
Helge Kristiansen SINTEF, Norway
Lennart Loljekvist Combitech Electronics AB, Sweden
Rogert Lindgren Alfa Laval Automation AB, Sweden
Johan Liu IVF, Sweden
Pontus Lundstrom Ericsson Components AB, Sweden
Bertil Weman Ericsson Telecom AB, Sweden
David Whalky Loughborough University of Technology, England
Petri Savonianen Helsinki University of Technology, Finland
Technical Committee
Chairman
Jan-Olof Anderson Saab Combitech Electronics AB, Sweden
Vice Chairman
Johan Liu IVF, Sweden
Heiner Bayer Siements AG, Germany
David W Bergman IPC-The Institute for Interconnecting and Packaging
Electronic Circuits, USA
Arun Chaudhuri Delco Electronics, USA
Dick Estes Epoxy Technology Inc., USA
Ken Gilleo Alpha Metals, USA
Jannick Guinet Schneider Electric S.A., France
O-D. Hennemann Fraunhofer-Institute for Applied Materials
Research, Germany
Manfred Hof Polytec GmBH, Germany
Jannes C. Jagt Philips, Centre for Manufacturing Technology, The
Netherlands
Jorma Kivilahti Helsinki University of Technology, Finland
Helge Kristiansen SINTEF, Norway
Jean H. Lapagnol Consulting Distribution, Services S.A., France
Pontus Lundstrom Ericsson Components, Sweden
Anders Marcelius VI, Sweden
James E. Morris State University of New York at Binghamton, USA
Harry M. Van Noort Philips, The Netherlands
Tomohisa Ota Hitachi Chemicals Co., Ltd., Japan
Diane Rudland Ablestik, England
Christoph Ruf VDI/VDE-Technology Centre for Information Technology,
Germany
Thomas Seidowski Dresden University of Technology, Germany
Ting-Ao Tang Institute of Microelectronics, Fudan University, China
David Williams Loughborough University of Technology,England
Sponsors: VDI/VDE (Germany) IPC (USA) VI (Sweden)
Return to Index
Conference Listing
ADVANCE PROGRAM
Workshop on Interconnections
within High Speed Digital Systems
May 14-15, 1995
Sante Fe, New Mexico
Sponsored by:
IEEE Lasers and Electro-Optics Society
IEEE Communications Society
in cooperation with IEEE Computer Society
SCOPE
The rapid evolution of integrated circuit technology has led to dramatic
improvements in the performance of advanced computing and communications
systems. Future applciations will require even more computational
and communications power. Even in today's systems, however,
interconnections are often a bottleneck to achieving higher performance.
The purpose of this workshop is to determine the interconnection
requirements of emerging computer and communications systems and to
evaluate advanced interconnection technologies in light of those
requirements. Because of the multi-disciplinary nature of the problem,
the workshop brings together researchers and practitioners with
expertise in a variety of fields including optical and electrical
interconnection technology, advanced system architectures, and the
algorithms and applications implemented in these systems. The format
of the workshop is highly interactive.
PROGRAM COMMITTEE
Chair: Rick Lytel, Akzo Nobel Electronic Products, Inc., Redwood City, CA.
Program Cochairs:
Anis Husain, Advanced Research Products Agency, Arlington, VA
Ted K. Woodward, AT&T Bell Laboratories, Holmdel, NJ.
Richard Carson, Sandia National Laboratories, Albuquerque
Local Arrangements:
Ireena Erteza, Sandia National Laboratoris, ALuquerque, NM.
Publicity:
Tulin Mangir, TM Associates, Santa Monica, CA
Int'l Liasons
Arne Wallers, Erricson Telecom AB, Stockholm, Sweden
Martin Goodwin, GEC-Marconi, Northants, United Kingdom
Osamu Wada, Fujitsu Laboratories, Atsugi, Japan
Steering Committee
Matthew Goodman, Bellcore, Red Bank, NJ
Tom Goblick, MIT Lincoln Labs, Lexington, MA
Mike Haney, George Mason University, Fairfax, VA
Working Group Chair
Fouad Kiamilev, University of North Carolina, Charlotte, NC
Working Group Committee
Howard Schlossberg, AFOSR, Bolling AFB, DC
Paul Haugsjaa, GTE Laboratories, Waltham, MA
Harold Stone, NEC Research Institute, Princeton, NJ
Marry Hibbs-Brenner, Honeywell Technology Center, Bloomington, MN
Dave Brady, University of Illinoise - Beckman Institute, Urbana, IL
Tony Ticknor, Kkzo Nobel Electronic Products, Redwood City, CA
Tom Cloonan, AT&T Bell Laboratories, Napervile, IL
Keith Goosen, AT&T Bell Laboratories, Holmdel, NJ
Don Channin, David Sarnoff Research Center, Princeton, NJ.
PROGRAM SUMMARY
Monday, May 15
Session 1: Applications
* Issues in future high performance microprocessor interconnect
systems development, Quat T. Vu, Intel Corp. Santa Clara, CA.
* Standardizing the high performance interconnect for parallel system
construction, Colin Whitby Stevens, SGS-Thomson Microelectronics,
Bristol, UK.
* Networking support of consumer multimedia, Alexander D. Gelman, Bellcore,
Morristown, NJ.
* Interconnect system design for intra-board high speed signal
transmission, Steve Leanheart, GTE Government Systems.
* Protocol extensions for asynchronous transfer mode security, Tom
Tarman, Sandia National Laboratories, Albuquerque, NM.
* Optoelectronic approaches to optical digital cross connect systems
applicable to very-high speed optical communication networks,
Toshikazu Sakano, NTT Optical Network Systems Laboratories,
Kanagawa, Japan.
Working Group Sessions I: Attendees break into groups of about 20
people to consider solutions to selected problems.
Working Group Sessions II: Problem study in working groups continues.
Working Group Sessions III: Problem study in working groups continues.
NOTE: The workshop emphasizes a highly interactive component of
researchers studying challenging problems and seeking technical
solutions to those problems.
Tuesday, May 16
Session 2: Technologies
* Hybrid smart pixels by flip-chip bonding to Si CMOS circuitry,
Keith Goosen, AT&T Bell Laboratories, Holmdel, NJ.
* Low cost, high performance photonic packaging, Robert A.
Boudreau, AMP Inc., Harrisburg, PA.
* III-V electronic circuit technology for optical interconnections,
Ken Pedrotti, Rockwell Science Center, Thousand Oaks, CA.
* The promise of silicon for high speed and low power, Behzad
Razavi, AT&T Bell Laboratories, Holmdel, NJ.
* Board-to-board optical interconnect products based on VCSELs,
Davis Hartman, Motorola, Tempe, AZ
* 3D silicon Technology, Jack Arnold, Irvine Sensors, Inc., Costa Mesa,
CA.
Working Group Session IV
Wednesday, May 17
Session 3: Keynote Presentations
* Trends and technology for multi-chip packaging, Nick Naclerio,
Advanced Research Projects Agency, Arlington, VA.
* Image processing and its impact on architecture, Harold S. Stone,
NED Research Institute, Princeton, NJ.
Working Group Wrap-up Session.
FURTHER INFORMATION:
Samantha H. Phillips
LEOS Executive Office
PO Box 1331
Piscataway, NJ 08855-1331
Fax: 908-562-1571
Phone: 908-562-3894
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SHORT COURSES
Semiconductor Bonding and Interconnection Technology
Joe C. Thompson Conference Center
Austin, Texas
May 31-June 2, 1995
Sponsored by: Dept. of Chemical Engineering, University of Texas at Austin.
OBJECTIVE:
Participants who attend this course will gain a full understanding of the
semiconductor wire bond process and how to assess the quality of the process
of bonded and assembled products. Using new, state-of-the-art analytical
techniques, the optimum and most reliable interconnection process can be
be developed. High frequency and power control will be emphasized.
PREREQUISITES:
Applicants to this course should possess a BS in engineering (any technical)
or its equivalent in engineering practical experience. A specific background
knowledge of semiconductor wire bonding is needed, as well as work related to
semiconductor wire bonding processing, packaging, and interconnection
assembly. People with job titles such as process technician, process
engineer for assembly and interconnection of semiconductors, failure
analysis engineer, and quality assurance engineer will find this course
informative.
OUTLINE:
* Overview of wafer fabrication and packaging
* Bond pad surface cleanliness
* Intermetallic phases
* Bond analysis
* Good bond guidelines
* Equipment related issues
* Material issues
* New technology
* Package-interconnection relationship.
FURTHER INFORMATION:
Registration:
Continuing Engineering Studies
College of Engineering
University of Texas at Austin
ECJ10.324
Austin, TX 78712
Phone: (512)471-3506
Course content: Prof. Trachtenberg at (512)471-1051.
Lodging (reduced rate until May 16, 1995):
Sheraton Austin Hotel
(512) 480-8181
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OTHER CONFERENCES OF INTEREST
The European Design and Test Conference - 1996
(From ASICs to Systems)
CNIT Conference and Exhibition Center
Paris, France
March 11-14, 1996
Sponsored by: EDAA, IEEE Computer Society, and ACM SIG-DA
SCOPE:
In the context of electronic and electromechanical products ranging from
integrated circuits through multichip modules and printed circuits to full
systems, the conference deals with:
1. The actual design of such products. Emphasis is on challenges and
experiences concerning the design of advanced electronic components
and systems.
2. The entire field of Design Automation and tools for such products.
Emphasis is on methods and tools employed in all aspects of the
use of computers for designing products. This includes fully
automatic as well as computer-guided approaches, data management
techniques, and user interfaces.
3. Testing of electronic products. This includes testing of digital,
mixed digital/analogue, and analogue circuits and systems, test
program development, test systems, and design for testability.
ED&TC covers the scope of the originally separate conferences EDAC and ETC.
INFORMATION:
Conference Secretariat: Exhibition Secretariat:
CEP Consultants Ltd. EDA Exihibitions Ltd.
43 Manor Place 31-33 High Holborn
Edinburgh EH3 7EB, UK London WC1V 6BD, UK
Phone: + 44 131 300 3300 Phone: + 44 171 404 0564
Fax: + 44 131 300 3400 Fax: + 44 171 831 2057
(100142.1323@compuserve.com)
General Chair: C. Lopez Barrio (barrio@tid.es)
Vice-general Chair: L. Eggermont
Programme Chair: P. Marwedel (marwedel@ls12.informatic.uni-dortmund.de)
Users Forum Chair: G. Saucier
DEADLINES AND KEY DATES
Submission of Manuscripts: Sept. 8, 1995
Notification of Acceptance: Nov. 10, 1995
Final Version of Manuscript Due: Dec. 15, 1995
Pre-Conference Tutorials: March 11, 1996
Conference Sessions: March 12-14, 1996
Exhibition: March 12-14, 1996
AREAS OF INTEREST
* Full System Design: Actual industrial or academic designs, applications
of ECAD; consumer electronics, telecommunications, automotive electronics
computers, electromechanical systems; power management.
* Digital ASIC as ASIP Design: Actual industrial or academic designs;
design of advanced chips, and chip-sets, experimentation with advanced
CAD tools and methodologies; use of tools and libraries, component
modeling; power management, package design.
* Design and Test of Analogue and Mixed Analogue/Digital Systems: Actual
industrial or academic designs,; simulation techiques and analytic
models for mixed systems; Synthesis and DfT techniques for mixed systems,
mixed-signal test.
* System Design Technologies: SPecification languages and paradigms; system
design techniques and tools; framework technologies; partitioning;
software-hardware codesign, code generation for embedded processors,
concurrent engineering, design modeling.
* Architectural Synthesis: Synthesis at the architectural level; high
level synthesis, architectural trade-offs, performance and cost driven
architectural synthesis, timing and power issues, VHDL for synthesis.
* Logic and Finite State Machine Synthesis: Combinational logic synthesis,
technology mapping, heirarchical controller synthesis, state assignment,
synthesis of testable controllers, performance-driven synthesis and power
control, PLD and FPGA synthesis, timing issues.
* Digital Simulation and Emulation: Advanced simulation techniques from
systems to circuit level, simulation languages (including VHDL and
Verilog), simulation accelerators, emulation techniques, embedded
hardware-software simulation, analytical models, emulation of large
systems.
* Formal Verification: Formal techniques and methods for verification,
design correctness, use of automatic theorem provers, symbolic
manipulation, formal specification languages, transformational
design, theory of BDDs.
* Layout Syntheis and Verification for VLSI, Boards, and MCMs: Automatic
place and route, performance and power driven layout, analogue and
digital cell layout rule checking and characterization, electrical
verification, modelling and characterization of on and off chip
interconnects.
* Design and Synthesis for Testability of Digital Systems: Internal scan,
macro test, boundary scan, built-in self test, IDDQ testability,
Proven < 50 PPM DfT schemes, testability planning for systems, ASICs,
embedded processors, and communications protocols, partitioning for
testability, system reliability issues.
* Test Program Development Tools and Techniques: Pattern generation,
test pattern generation for memories, fault simulation, expert systems,
inductive fault analysis, languages and standards.
* Component, MCM, Board and System Testing: ATE hardware and software,
test-pattern application, fixturing, pin electronics, diagnostic
techniques, VXI bus systems, IDDQ-test-hardware, functional and structural
approaches and safety-critical appliations, 1149.1, 1149.2, 1149.4,
microcomputer based self-test.
* Methods and Tools for the Design of Microsystems: CAD tools for the
design and test of micromechanical systems, microengines and sensors.
SUBMISSION OF PAPERS
Two different categories of papers are distinguished. Contact the
Conference Secretarial below for instructions regarding perparation
of either a (1) submission for the formal proceedings or (2) submission
for the User's Forum. Detailed formating specifications must be followed
for the first category (formal proceedings)
SUBMIT MANUSCRIPTS TO
Conference Secretariat
CEP Consultants Ltd.
43 Manor Place
Edinburgh, EH3 7EB
United Kingdom
Phone: +44 131 300 3300
Fax: +44 131 300 3400
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Return to Listing of Other Conferences of Interest
ANNOUNCEMENT
International Mixed Signal Testing Workshop
Grand Hotel de Paris in Villard de Lans
Grenoble, France
June 20 - 22, 1995
Sponsored by: IEEE Computer Society, Test Technology Technical Committee
SCOPE
This workshop aims at providing a place to discuss Mixed Signal Testing and
related areas such as BIST, design for test, concurrent testing of analog
and mixed circuits and boards. The Workshop will be held annually,
moving between Europe, the US, and Canada. The Workshop is sponsored
by the IEEE Computer Society Test Technology Technical Committee, in
cooperation with the European Test Technology Technical Committee
(ETTTC) and the Network of Researchers in Mixed Signal and Analog
Testing (NORMATE).
TOPICS (include but are not limited to)
* Mixed-signal (analog/digital) testing
* Analog Circuit Testing
* Concurrent testing of mixed-signal and analog circuits and boards
* Disign for test and BIST of mixed signal and analog circuits and
boards.
INFORMATION
B. Kaminska
Ecole Polytechnique de Montreal
2900 Boul. Edouard Montpetit
CP 6079, succ. A, Montreal, PQ
Canada H3C 3A7
Tel: +1 514 340 4270
Fax: +1 514 340 4147
Email: bozena@VLSI.POLYMTL.CA
PEOPLE
General Chair: B. Courtois, TIMA/INPG, Grenoble
Program Chair: B. Kaminska, Ecole Polytechnique de Montreal
IEEE liaison: M. Soma, Univ. of Washington
ETTTC liaison: P. Prinetto, Politecnico di Torino
NORMATE Liaison: M. Ohletz, University of Hannover
Program Committee:
J. Abraham: Univ. of Texas at Austin
J. Huertas-Diaz: Univ. of Sevilla
B. Kaminska: Ecole Polytechique de Montreal
M. Nicolaidis: TIMA/INPG, Grenoble
M. Ohletz: Univ. of Hannover
A. Osseiran: Ecole Polytecnique Federale de Lausanne
M. Soma: Univ. of Washington
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Return to Listing of Other Conferences of Interest
BOOKS
TITLE: Plastic Encapsulated Microelectronics: Materials, Processes, Tests,
Reliability, and Applications.
AUTHORS: M. Pecht, L. Nguyen, and E. Hakim (Editors).
PUBLISHER: John Wiley & Sons
605 Third Avenue, New York, NY 20158-0012
Tel: (212) 850-6000.
SUMMARY:
The past twenty years have seen many important advances in
plastic encapsulated microcircuit (PEM) technology. Thanks to
new packaging materials, improved design and manufacturing
processes, and other important developments, PEMs are now a
dependable and cost-effective option for a wide range of
electronic systems applications. Nevertheless, there continue to
be challenges to the design and use of PEMs.
For the first time, there is a comprehensive, critical
review of the state of the art in PEMs and the assemblies that
incorporate them. The most timely book on the subject, it
provides professionals with a systematic, scientific exploration
of all crucial technology and reliability issues concerning the
manufacture and use of PEMs, with special attention to
environment-specific applications. Among the important topics
covered in detail are:
- Encapsulating materials -- composition, properties and
characteristics;
- Fabrication technology -- with an in-depth look at potential
defects that can occur during assembly
- Failure mechanisms -- sites and modes;
- Failure analysis techniques -- relative strengths and
weaknesses;
- Screening techniques -- the pros and cons of using these
technique for reliability conformance and quality
improvement and their correlative defects; and
- Qualification and life testing techniques -- their
effectiveness in simulating use conditions.
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Return to Listing Recent Books
TITLE: Multichip Modules & Related Technologies: MCM, TAB and COB Designs
AUTHORS: Gerald Ginsberg and Donald Schnorr.
PUBLISHER: McGraw-Hill Inc.
11 West 19th Street, New York, NY 20158-0012
Tel: +1 800-2-MCGRAW
Fax: +1 212 337 4092
SUMMARY:
Surface mount technology (SMT) revolutionized the electronic packaging
field in the 80s. Now, while many manufacturers are still rushing to
retool for SMT, three new technologies are taking the industry by
storm: multichip module (MCM), tape automated bonding (TAB) and
chip on board (COB) packaging. Capable of producing results that
are fifty percent lighter, fifty percent smaller, and fifty percent
cheaper than SMT, these leading edge technologies are bound to have
an enormous impact on a broad spectrum of applications, from
aerospace and communications to advanced computer and control technologies.
1994, 320 pp., $55.00
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TITLE: Multichip Module Design, Fabrication and Testing
AUTHORS: James J. Licari.
PUBLISHER: McGraw-Hill Inc.
11 West 19th Street, New York, NY 20158-0012
Tel: +1 800-2-MCGRAW
Fax: +1 212 337 4092
SUMMARY:
The advent of multichip modules (MCMs) is revolutionizing the ways in
which electronic systems and equipment are designed, tested, and
manufactured. Now, one of its pioneers has written the first book
that not only describes MCM technology but also shows designers how
to use it in practice. This guide covers such practical issues as
electronics testing, rework procedures, and failure modes and mechanisms.
1994, 350 pp., $55.00
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Return to Listing Recent Books
TITLE: Design Guidelines for Surface Mount and Fine Pitch Technology, 2nd Edition
AUTHORS: Vern Solberg
PUBLISHER: McGraw-Hill Inc.
11 West 19th Street, New York, NY 20158-0012
Tel: +1 800-2-MCGRAW
Fax: +1 212 337 4092
SUMMARY:
Advances in surface mount technology in the past few years have had
a significant impact on the way in which electronic products are
manufactured. The second edition of this popular guide brings readers
right to the forefront of this rapidly evolving field. Still the only
book to focus on design for manufacturing of surface mount PC boards,
the new edition features the latest breakthroughs in fine paitch and
ball-grid-array devices. As before, readers will find step-by-step
guidance - from one of the industry's best-known experts - for developing
the most cost effective products possible using SMT.
1995, 250 pp., $45.00
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TITLE: Hybrid Microelectronics Handbook, 2nd Edition
AUTHORS: Jerry E. Sergent and Charles A. Harper
PUBLISHER: McGraw-Hill Inc.
11 West 19th Street, New York, NY 20158-0012
Tel: +1 800-2-MCGRAW
Fax: +1 212 337 4092
SUMMARY:
A co-publication with ISHM, this substantial revision provides the
most current data and guidelines to those involved with the design,
manufacture, and use of hybrid microelectronics. A distinguished
groupe of experts in the field bring readers thoroughly up to date
on topics ranging from basic design and development techniques through
testing, manufacturing, and quality control issues.
1995, 750 pp., $89.50
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JOBS
Submitted by: K. "JAY" Jayaraj
jayaraj@world.std.com
Foster-Miller has an immediate opening for a senior engineer in the
electronic/optoelectronic packaging area. Responsibilities include:
generating new and innovative packaging concepts, writing proposals for
external funding, project management and lead/coordinate the work of
junior engineers and outside vendors.
Qualifications:
Ph.D. or M.S. (with atleast 4 years of experience) in a related field
from a university with an established program in electronic packaging.
Knowledge of advanced packaging principles and technologies including,
multichip modules for digital, microwave and optoelectronic
applications. Excellent written and oral communication skills.
Only US citizens or permanent residents need to apply
Foster Miller is a 39 year old technology development company located in
the Boston Metro area. We offer a competitive compensation package and a
challenging yet rewarding work atmosphere. Foster Miller currently
employs about 250 people (including support personnel)
Please send your resume to:
Dr. K. "JAY" Jayaraj
195 Bear Hill Road
Waltham, MA 02154
FAX: 617-290-0693
Internet: jayaraj@world.std.com
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