IEEE CPMT INFORMATION
- Table of Contents:
Upcoming and current issues of IEEE Trans
Advanced Packaging < http://www.ieee.org/pub_preview/cpmtb_toc.html>
CONFERENCES AND WORKSHOPS
Workshop: Reliability of Electronics Packaging
Loughborough University of Technology
21st June 1995
Hosted by: International Electronics Reliability Institite (IERI)
Submitted by: J JONES
On the 21st June 1995, the International Electronics Reliability Institite
(IERI) plans to hold the third in a series of one day workshops. The topic
is "Reliability of Electronics Packaging" and IERI are pleased to have as
guest speaker Professor Nihal Sinnadurai, Professor of Microelectronics at
Middlesex University.
Professor Sinnadurai will present state of the art thinking on the packaging
of electronic components with particular accent on packaging for integrated
circuits. The Workshop will also contain sessions addressing other relevant
topics.
The Workshop will take place in the Department of Electronic and Electrical
Engineering at Loughborough University of Technology on Wednesday 21st June
1995. Morning and afternoon refreshments and a buffet lunch are included in
the registration price of 9C200 per attendee. Please make cheques payable to
Loughborough University, or contact IERI for details of alternative payment
methods.
Details of overnight accommodation close to the Workshop venue can be
provided. Please contact IERI for further details on:
TEL. +44 (0)1509 222849
FAX. +44 (0)1509 222854
Or Send e-mail to
J.A.Jones@lut.ac.uk
or
S.Dart@lut.ac.uk
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Workshop on Area Array Packaging Technologies
(Flip Chip and Ball Grid Arrays)
Loughborough University of Technology
Berlin, Germany
November 13 - 15, 1995
Organized by: Fraunhofer Einrichtung IZM, Berlin
German Chapter of IEEE-CPMT
Submitted by: D. Whalley
GENERAL INFORMATION
The Fraunhofer Einrichtung IZM, Berlin, and the forming German Chapter of
IEEE-CPMT (Components, Packaging, and Manufacturing Technology) Society are
jointly organizing a Workshop on Flip Chip and Ball Grid Array Packaging
Technologies. The Workshop, which is supported by the European NETPACK
OFFICE, will take place in Berlin the week following the PRODUCTRONICA
exhibition (Munich). The Workshop will be conducted in single, sequential
sessions so that those attending will be able to hear every paper. Most
papers will be 20 minutes long with time for questions and discussions.
TECHNICAL COMMITTEE
Karl-Heinz Arnold, DLR (D)
Eckhardt Bihler, STP (D)
Lubomir Cergel, Motorola (CH)
Nicholas Chandler, GEC Marconi (GB)
Paul Collander, Nokia (SF)
Karl Deckelmann, W.C. Heraeus (D)
Richard B. Hammer, IBM (USA)
Subash Khadpe, STC (USA)
Robert C. Marrs, Amkor (USA)
Elisabeth Reese, VDI/VDE-IT (D)
Herbert Reichl, FhG-IZM / TU Berlin (D)
Horst Richter, Alcatel SEL (D)
Maurice G. Sage, BPA (GB)
Martin Seyffert, Blaupunkt (D)
Yves Stricot, Bull (F)
N.J.A. Van Veen, Philips (NL)
PAPER SUBMISSION
An extended abstract supplemented with up to four of your most important
figures should be sent either to:
Dr. Elke Zakel
Fraunhofer Einrichtung IZM - Berlin
Gustav-Meyer-Allee 25
13355 Berlin, Germany
phone: ++49 - 30 - 314 - 72896
Fax: ++49 - 30 - 314 - 72835
or to:
Dr. Hermann Oppermann
Microperipheric Center
Technical University Berlin,
Secr. TIB 4/2-1
Gustav-Meyer-Allee 25
13355 Berlin, Germany
phone: ++49 - 30 - 314 - 72832
Fax: ++49 - 30 - 314 - 72835
email: oppe1270@mailszrz.zrz.TU-Berlin.DE
Abstracts must be received by July 31, 1995. The abstracts will be included
in a conference handout, which will be given to all those attending. Authors
will be notified of paper acceptancy by end of August, 1995.
TOPICS
Flip Chip Technology
- Bumping
- Low cost technologies
- Soldering, fluxless processes
- Thermocompression bonding
- Adhesive bonding
- Underfill, encapsulation
- Flip chip on MCM-L, MCM-D, and MCM-C substrates
- Flip chip on rigid and flexible printed wiring boards
- Flip chip on glass
- Burn in, test and repair
- Reliability
- Electrical and mechanical simulation
- Costs
- Applications
- Equipment
Ball Grid Array
- Design rules
- Plastic BGA
- Ceramic BGA
- Tape BGA
- Column grid array
- Assembly
- Inspection and testing
- Electrical and thermal performance
- Single chip and multi-chip packages
- Process control
- Yield issues
- Repair
- Applications
- Equipment
- Reliability (board level assembly, environmental issues including
moisture effects) - Standardization of packages and test methods
Chip Sized Packages
- Packaging concepts
- Interconnection technology
- Performance
- Testing
- Applications and costs
- Reliability
- Advantages compared to FC assembly of bare die and BGA packages
EXHIBITS
The conference is interested in corporate sponsors and technical exhibits
relating to the theme of the Workshop during the conference. A vendors
reception will be held during the conference. The list of exhibitors and
sponsors will be included in the final program. For further information
please contact Dr. Elke Zakel.
OFFICIAL LANGUAGE
The official language of the Workshop is English. All presentations,
including discussions and submitted material must be in English.
GENERAL
For information on other activities of the forming German Chapter of the
IEEE-CPMT Society please contact Dr. Elke Zakel.
---------------------------------------------------------------
AREA ARRAY PACKAGING TECHNOLOGIES
Workshop on Flip Chip and Ball Grid Arrays
November 13 - 15, 1995, Berlin, Germany
Please reply to:
Dr. Elke Zakel
FhG-IZM
Gustav-Meyer-Allee 25
D-13355 Berlin
GERMANY
o I am planing to attend the Workshop
o I would like to contribute to the Workshop as a speaker,
enclosed you receive my abstract
o I would like to contribute to the vendors exhibition
o I am interested in the German Chapter
of the IEEE-CPMT Society which is in formation
Name:
Company/Institution:
Address:
Phone:
Fax:
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FIFTH INTERSOCIETY CONFERENCE ON THERMAL PHENOMENA IN ELECTRIC SYSTEMS
"ITHERM"
Orlando Florida
May 29 - June 1, 1996
Sponsored by: IEEE, ASME, ISHM, and NIST
Submitted by: Paul A. Baltes
SUMMARY
ITHERM is a transdisciplinary forum for exploring progress in
understanding, analyzing, and modeling thermal transport processes and
thermally induced failures in all aspects of electronic systems. The
emphasis of miniaturizing electronic systems continues to drive the need
for more efficient thermanl management, both at the component and system
levels. For reducing lead time on new products, the emphasis on
concurrent design of electronic packaging has dramatically increased.
Simultaneous engineering is necessary by mechanical, electrical, and
materials engineers. In addition to paper presentations, ITHERM V will
include:
* Exhibits by hardware/software vendors.
* Keynote lectures by prominent speakers.
* Panels on pertinent topics with invited speakers.
* Sessions where industry participants present current problems.
* Short courses on Air Cooling, Application to CFD to Electronic
Cooling.
Papers are solicited in the following general areas:
THERMAL ENGINEERING IN INTEGRATED DESIGN SYSTEMS
* Application of numerical, experimental, and analytical thermal
modeling and methodology in Integrated Design Systems.
* Computer-Aided Thermo/Mechanical Engineering - Design
Integration and Design Tools.
PHENOMENA IN SEMICONDUCTOR PROCESSING & PACKAGE FABRICATION
* Temperature and stress distributions in crystal growth,
bonding, lamination, soldering, and other production processes.
THERMAL CONTROL OF COMPUTER SYSTEMS
* Single and multiphase convective cooling of components.
* Numerical, analytical, and experimental characterization of
heat sinks.
* Numerical and analytical characterization of computer systems
and components, such as screens, grills, and fans.
* Thermal issues of micromachines
* Interfacial phenomena, such as contact resistance.
* Thermal issues of portable electronics
TEMPERATURE DEPENDENT FAILURES
* Thermally induced stresses.
* Void and crack propagation.
* Solder joint failures
* Failure mechanism at low temperatures.
THERMAL PHENOMENA IN PERIPHERAL EQUIPMENT
* Flow and temperature fields in co-rotating disks and disk
drives.
* Thermal issues in hard-drive assemblies, optical recording
systems, thermal printing heads, and dot-matrix heads.
* Heat transfer across sliding surfaces in contact.
EMERGING PROBLEMS IN AUTOMOTIVE ELECTRONICS
_____________________________________________________________________
To submit a paper, send a 250 word abstract plus key figures by August 15,
1995.It must clearly describe the nature, scope, content, organization, key
points, and significance of the proposed paper. If using e-mail, post
script files will be accepted. The paper must consist of work or results
not published previously. Key dates are as follows:
Abstract submission - August 15, 1995
Author notification - September 10, 1995
Manuscrits due - November 1, 1995
Paper acceptance - January 5, 1996
Camera-ready papers - February 15, 1996
The language for the conference and its publications is English. ITHERM
is sponsored by IEEE, ASME, ISHM, and NIST. Membership in these
organizations is not required to present a paper or to attend the conference.
MAIL ALL ABSTRACTS AND SUBSEQUENT PAPERS TO THE CONFERENCE ADMINISTRATOR AT:
ENGINEERING PROFESSIONAL DEVELOPMENT
BOX 9, HARVILL BUILDING, RM 235
SECOND & OLIVE STREETS
UNIVERSITY OF ARIZONA
TUCSON, AZ 85721-0076
PHONE: (520) 621-3054
FAX: (520) 621-1443
E-MAIL: baltes@bigdog.engr.arizona.edu
Updated ITHERM information may be found on the web at:
http://www.research.digital.com/wrl/projects/ITHERM/ITHERM.html
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Int'l Electronics Packaging Conference and Exhibition
San Diego, California
September 24-27, 1995
General Information
The conference will feature 15 technical sessions, 5 professional
education courses, a technical forum, vender sessions, and a 100
booth exhibition.
Summary of Techical Sessions
o Innovations in advanced packaging.
o IC packaging solutions.
o Thermal management I: modeling and simulation.
o Multichip: module applications.
o Packaging materials.
o Packaging reliability.
o Chip interconnect technology.
o Electrical modeling and simulation.
o Ceramic packaging technology.
o Thermal management II: packaging and measurement.
o BGA I: New BGA packaging development.
o Packaging for surface mount.
o Advanced system packaging.
o BGA II: thermal and reliability analysis.
o Packaging for information highways.
Further Information
Contact IEPS, PO Box 43, Wheaton, IL 60189-0043
Tel: (703)260-1044 (800)990-4377
Fax: (708)260-0867
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Surface Mount International
San Jose, California
Aug 27 - 31, 1995
Sponsored by EIA, IPC, Miller Freeman, Inc., and Surface Mount
Technology Association.
General Information
This year's conference theme, "Design for Excellence", will explore
technology trends in the design and manufacturing of electronic products.
This year's program introduces such topics as ball grid arrays, chip-
on-board, and PCMCIA assemblies. Subjects addressed at the conference
include MCM-Ls, thermal characterization, and X-ray inspection.
Now in its fifth year, Surface Mount International has evolved into the
leading conference and exhibition dedicated to surface mount and related
technologies. The conference includes over 125 previously unpublished
papers from some of the leading researchers in industry and academia.
In addition, 20 tutorials and 7 workshops enhance the technical program.
Because Surface Mount International is focused on surface mount
technologies, there is a concentrated attention on issues and technologies
such as ball grid array, MCM-Ls, conductive adhesives, PC cards (PCMCIA),
and chip-scale packaging.
TUTORIALS
T.1: Surface mount technologies: principles and practices.
T.2: Introduction to MCM-L technology.
T.3 Known good die?
T.4 Surface mount attachment reliability: testing and modeling principles.
T.5 Improving the solder process through defect analysis.
T.6 Robust product and process design with design of experiments (DoE).
T.7 Conductinve adhesives and other polymer-based electronic material for
SMT and COB assembly.
T.8 Ball grid array technology.
T.9 Flexible circuits: a packaging technology with wide applications.
T.10 SMT manufacturing process control.
T.11 Design guidelines for high-speed PCB applications
T.12 An overview of BGA and fine-pitch peripheral interconnection.
T.13 Mastering and implementing BGA rework.
T.14 SMT compatible chip on board for MCM-L applications
T.15 SMT/FTP inspection, workmanship guidelines, and rework/repair techniques
T.16 Reliability and yield problems for wire bonding in microelectronics.
T.17 Modern techniques to reduce test costs
T.18 Cost-effective, low-volume chip on board assembly.
T.19 Automated low-volume surface mount assembly.
T.20 Lead-free soldering.
TECHNICAL SESSIONS
PKG.1 International developments in chip-size packaging (part 1)
PKG.2 International developments in chip-size packaging (part 2)
PKG.3 Flip-chip technology developments
PKG.4 Flip chip on flex
PKG.5 Implementing chip on board assembly process
PKG.6 Area array attachment materials and processes
PKG.7 Advanced materials
BGA.1 BGA packages
BGA.2 BGA design considerations
BGA.3 BGA processes
BGA.4 BGA manufacturing (part 1)
BGA.5 BGA reliability (part 1)
BGA.6A BGA manufacturing (part 2)
BGA.6B BGA reliability (part 2)
SOL.1 Developments in soldering methodology
SOL.2 Understanding solderability testing
SOL.3 Solder materials
SOL.4 Implementing solderability testing techniques
SOL.5 Alternatives to solder (conductive adhesives)
MFG.1 Manufacturing strategies
MFG.2 Manufacturing technologies for high-density products
MFG.3 Manufacturing reliability concerns
MFG.4 Design for manufacturability
MFG.5 Manufacturing process (part 1)
MFG.6 Manufacturing process (part 2)
MFG.7 Optimizing soldering processes for SMT
COM.1 Component technology
SMC.1 Design for success (part 1)
SMC.2 Design for success (part 2)
PCB.1 PCB protective coatings
TST.1 Test as a process monitor
CNA.1 Consortia activities (part 1)
CNA.2 Consortia activities (part 2)
PCC.1 PC card design
PCC.2 PC card manufacturing (part 1)
PCC.3 PC card manufacturing (part 2)
WORKSHOPS:
W.1 Solving common problems in manufacturing
W.2 Harnessing the ball grid array stampede
W.3 Land patterns
W.4 Planar resistor technology: design and processing
W.5 PC card design guidelines
W.6 SMT rework: theory, methods and applications
W.7 Joint industry solder specifications
More Information
Contact Miller-Freeman, 600 Harrison Street, San Francisco, California
Tel: (415)905-2200
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Device-To-Package Interconnects
(Session A)
Cleveland, Ohio
October 30, 1995
Sponsored by: Electronic Materials and Processing Division
(EM&P) of ASM International
Talks:
1. Effect of aging of fatigue crack growth at Sn-Pb/Cu interfaced.
D. Yao and J.K. Shang, Univ. of Illinois at Urbana Champaign.
2. Structure and process to provide high density packaging
interconnections. U.M. Ahmad and S.K. Ray, IBM Microelectronics.
3. Creep and contitutive equations of high temperature solder alloys.
J. Liang, N. Golhardt, and P.S. Lee, Rockwell Internations Automation.
4. Structural and materials characterization of tape automated bond
electrical interconnections. D.C. Keezer and A.S. Slater-Haase,
University of South Florida.
5. Advanced surface mount array interconnects for high density packages.
U.M. Ahmad and B.Z. Hong, IBM Microelectronics.
6 Influence of microstructure on electromigration induced void and
hillock growth in thin film tin and tin-copper bilayers.
Y. Xu, Georgia Institute of Technology.
For further information, contact
A. Elshabini-Riad, Tel: (703)231-4469 Fax: (703)231-3362
or
D.C. Keezer, Tel: (813) 974-3610 Fax: (813)974-3610
or
J. Liang, Tel: (414)382-4273 Fax: (414)382-3500
or
B.R. Livesay, Tel: (404)664-8742 Fax: (404)410-0122
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Electronic Materials Characterization
(Session B)
Cleveland, Ohio
October 30, 1995
Sponsored by: Electronic Materials and Processing Division
(EM&P) of ASM International
Talks:
1. Interface and intermetallic interactions mechanical characterization
of thin cast solder material. B.R. Livesay, Livesay Scientific
Services, Y. Xu, Georgia Institute of Technology, G.B. Freeman,
Materials Analytical Services.
2. PA46, a low cost polyimide alternative. J. Koenen, DSM Engineering
Plastics.
3. Electrical evaluation of electronic materials. F. Barlow, S. Riad,
W. Su, and A. Elshabini-Riad, VPI.
4. Electrical performance of alumina and aluminum nitride substrates.
A.P. Agrawal, IBM Microelectronics.
5. A study of thermoplastic materials in connectors. J. de Graff and R.
Glaser, DSM Engineering Plastics.
For further information, contact
B.R. Livesay, Tel: (404)664-8742 Fax: (404)410-0122
or
Y. Murty, Tel: (717)231-3184 Fax: (717)231-3184
or
F. Barlow, Tel: (703)231-4469 Fax: (703)231-3362
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The European Design and Test Conference
(from ASICs to Systems)
Paris, France
March 11-14, 1996
Sponsored by: EDAA, IEEE Computer Society, and ACM SIG-DA
Submitted by Bernard Courtois, EDAA Charman
General Information:
In the context of electronic and electromechanical products ranging from
integrated circuits through multi-chip mocules and printed circuit
boards to full systems, the conference deals with
o The actual design of such products. Emphasis is on challenges and
experiences concerning the design of advanced electronic
components and systems.
o The entire field of Design Automation and tools for such products.
Emphasis is on methods and tools employed in all aspects of the
use of computers for designing products. This includes fully
automatic as well as computer-guided approaches, data
management techniques, and user interfaces.
o Testing of electronic products. This includes testing of digital,
mixed digital/analogue and analogue circuits and systems, test
program development, test systems and design for testability.
AREAS OF INTEREST:
Original technical papers on (but not limited to) the following topics are
invited.
1. Full system design
2. Digital ASIC and ASIP design
3. Design and test of analogue and mixed analogue/digital systems
4. System design technologies
5. Architecture synthesis
6. Logic and finite state machine synthesis
7. Digital simulation and emulation
8. Formal verification
9. Layout synthesis and verification for VLSI, boards, and MCMs
10. Design and synthesis for testability of digital systems
11. Test program development tools and techniques
12. Component, MCM, board and system testing
13. Methods and tools for the design of microsystems.
Deadlines and key dates
Submission of manuscripts: September 8, 1995
Notification of acceptance: November 10, 1995
Final version of manuscript due: December 15, 1995
Pre-conference tutorials: March 11, 1996
Conference sessions: March 12-14, 1996
Exhibition: March 12-14, 1996
Information Regarding Manuscript Submission
Conference Secretariat
CEP Consultant Ltd.
43 Manor Place
Edinburgh, EH3 7EB, UK
Tel: +44 131 300 3300 Fax: +44 131 300 3400
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6th Annual Electronics Packaging Symposium
(Critical Issues in Packaging Assemblies)
Binghamton University, Binghamton, NY
July 13-14, 1995
Sponsored by: Watson School of Continuing Education, IEPS,EIA/MCM
IEEC, ISHM, and SMTA
GENERAL INFORMATION
The symposium focuses on a cross section of critical technologies
in the design and manufacture of packaging assemblies. Design and
assembly issues in such technologies as ball grid array, flip chip --
high density substrates, wireability, wirebond, materials options and
reliability are but a few of the important topics explored in this
year's symposium. The 1995 program examines several leading
technologies from the standpoint of how they contribute to competitive
positioning in the global marketplace.
FURTHER INFORMATION:
Office of Continuing Education
T.J. Watson School of Engineering and Applied Science
Binghamton University
PO Box 6000
Binghamton, NY 13902
Tel: 607-777-2154
Fax: 607-777-4411
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2nd Multi-Chip Module Test Advanced Technology Workshop
Napa, California
Sept. 10-13, 1995
Sponsored by: ISHM, Microelectronics Society, and IEEE CS
Test Technology Technical Committee.
GENERAL INFORMATION
The MCM Test Advanced Technology Workshop explores state of the art
MCM test cncepts, trends, and practices. The workshop focuses on test,
diagnosis, and repair challenges for multi-chip modules. MCC's "Known
Good Die Forum" will be held in conjunction with the workshop at the
same site on Sept. 14, 1995. Topics for workshop presentation include
o Design-for-testability
o Economics and cost analysis
o Fault diagnosis
o Known good die
o MCM burn-in
o Module level test
o Multi-chip built-in self-test
o Repair and rework
o Substrate Testing
o Test and instrumentation
o Trouble shooting
o Testing strategies
FURTHER INFORMATION:
Janet Kingston
ISHM
1850 Centennial Park Drive, Suite 105
Reston, VA 22091
Tel: 703-758-1060
Fax: 703-758-1066
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OTHER CONFERENCES
EIGHTH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS
Cannes, Cote d'Azur, France
September 13-15, 1995
Co-sponsored by the ACM/SIGDA and IEEE/DATC in cooperation
with IFIP/WG 10.5, SGS-Thomson Microelectronics, France
Telecom and TIMA/CNRS-INPG-UJF
Submitted by B. Courtois
Co-sponsored by the ACM/SIGDA and IEEE/DATC in cooperation
with IFIP/WG 10.5, SGS-Thomson Microelectronics, France
Telecom and TIMA/CNRS-INPG-UJF
GENERAL INFORMATION
This symposium is the eighth in a series of high-quality technical
forums. It is the continuation of the previous High-Level Synthesis
workshop and symposium events. The symposium is oriented
towards design automation professionals and presents the latest
results in emerging synthesis and system design technologies. This
includes: System-level synthesis, programmable processor based
design and software synthesis, hardware-software co-design and
behavioral synthesis.
ADVANCE PROGRAM
TUESDAY SEPTEMBER 12
06:00 PM - 08:00 PM Registration
07:00 PM - 09:00 PM Reception
WEDNESDAY SEPTEMBER 13
8:30 AM Opening, Welcoming remarks: Pierre Paulin/Farhad Mavaddat
9:00 AM Invited talk: Multi-media system design (to be confirmed)
10:00 AM Session 1: HW/SW codesign
"Sensitivity-Driven Co-Synthesis of Distributed Embedded
Systems" Ti-Yen Yen, W. Wolf - Princeton University, USA
"Multiple-Process Behavioral Synthesis for Mixed
Hardware/Software Systems" J.K. Adams, D.E. Thomas - Carnegie
Mellon University, USA
"An Approach to Interface Synthesis" J. Madsen, B. Hald -
Technical University of Denmark, Denmark
"The Chinook Hardware/Software Co-Synthesis System" P.H.
Chou, R.B. Ortega, G. Borriello - University of Washington, USA
"Clustering for Improved System-Level Functional Partitioning" F.
Vahid - University of California, Riverside, D.D. Gajski -
University of California at Irvine, USA
12:00 AM Focus groups: Workgroup discussion periods involving all attendees
1:00 PM Lunch
2:30 PM Session 2: Code generation and software synthesis
"Optimal Code Generation for Embedded Memory Non-
Homogeneous Register Architectures" G. Araujo, S. Malik -
Princeton University, USA
Optimal Register Assignment to Loops for Embedded Code
Generation" D.J. Kolson, A. Nicolau, N. Dutt - University of
California at Irvine, USA, K. Kennedy - Rice University, USA
"Real-time Multi-tasking in Software Synthesis for Real-Time
Information Processing Systems", F. Thoen - IMEC, Belgium, M.
Cornero - SGS-Thomson, France, G. Goossens - IMEC, Belgium,
H. De Man - Katholieke Universiteit Leuven, Belgium
"Time-constrained Code Compaction for DSPs", R. Leupers, P.
Marwedel - University of Dortmund, Germany
"Industrial Experience Using Rule-driven Retargetable Code
Generation for Multimedia Applications", C. Liem - TIMA
Laboratory and SGS-Thomson Microelectronics, France, P. Paulin,
M. Cornero- SGS-Thomson Microelectronics, France, A.A. Jerraya
- TIMA Laboratory, France
4:30 PM Panel: "System synthesis research and industry expectations:
how do we converge?" Moderator: Pierre Paulin, SGS/Thomson, France
Panelists:
Joseph Borel, SGS/Thomson, France
Theo Claasen, Philips, Netherlands
Leon Cloetens, Alcatel, Belgium
Hugo De Man, Katholieke Universiteit Leuven, Belgium
Dan Gajski, University of California at Irvine, USA
Ron Miller, Synopsys, USA
THURSDAY SEPTEMBER 14
8:30 AM Invited Talk: Real-Time System Specification and Verification,
Joseph Sifakis, VERIMAG, France
9:30 AM Session 3: Behavioral synthesis
"Synthesis of Pipelined DSP Accelerators with Dynamic
Scheduling", P. Schaumont, B. Vanthournout, I. Bolsens -
IMEC/VSDM, Belgium, H. De Man - Katholieke Universiteit
Leuven, Belgium
"An Exact Solution Methodology for Scheduling in a 3D Design , S.
Chaudhuri, S.A. Blythe, R.A. Walker - Rensselaer Polytechnic
Institute, USA
"Procedure Exlining: A Transformation for Improved System and
Behavioral Synthesis", F. Vahid - University of California,
Riverside, USA
"Array Mapping in Behavioral Synthesis", H. Schmidt, D. Thomas -
Carnegie Mellon University, USA
"On the use of VHDL-based behavioral synthesis for telecom ASIC
design", M. Genoe, P. Vanoostende, G. Van Wauwe - Alcatel-Bell,
Belgium
11:30 AM Focus groups: Consolidation of results
2:30 PM Session 4: Low-power and estimation techniques for behavioral and
system level synthesis
"Scheduling and Resource Binding for Low Power", E. Musoll,
J.Cortadella - Polytechnic University of Catalonia, Spain
"Power Analysis and Low-Power Scheduling Techniques for
Embedded DSP Software", M. Tien-Chien Lee - Fujitsu
Laboratories of America, USA, V. Tiwari, S. Malik - Princeton
University, USA, M. Fujita - Fujitsu Laboratories of America, USA
"A Path-Based Technique for Estimating Hardware Runtime in
HW/SW Cosynthesis", J. Henkel, R. Ernst - Technische Universit
Braunschweig, Germany
"A Comprehensive Estimation Technique for High-Level Synthesis,
S. Yong Ohm, F.J. Kurdahi, N. Dutt, M. Xu - University of
California, Irvine, USA
"Profiling in the ASP Codesign Environment", M.F. Parkinson,
P.M. Taylor, S. Parameswaran - University of Queensland, Australia
4:30 PM Panel: "How do we reduce digital system power at the system level?"
Moderator: Paul Landman, TI, Dallas, USA
Panelists:
Francky Catthoor, IMEC, Belgium
Theresa Meng, Stanford Univ, USA
Tobias Noll, Univ. Aachen
Stefaan Note , Philips/ITCL
Jan Rabaey, U.C.Berkeley, USA
FRIDAY SEPTEMBER 15
8:30 AM Session 5: Design methods for HW/SW systems.
"WWW Based Structuring of Codesigns", P.G. Plger, J. Wilberg,
M. Langevin - GMD-SET, Germany, R. Camposano - Synopsys,
Inc., USA,
"System Level Verification of Video and Image Processing
Specifications" , H. Samson, F. Franssen, F. Catthoor, H. De Man
- IMEC, VSDM Division, Belgium
"Synthesis of System-Level Communication by an Allocation-Based
Approach", J.M. Daveau, T. Ben Ismail, A.A. Jerraya - TIMA
Laboratory, France
"Modeling and Simulation of Heterogeneous Real-Time Systems
Based on a Deterministic Discrete Event Model", J. Teich, E.A. Lee
- University of California at Berkeley, USA, L. Thiele - ETH
Zurich, Switzerland
"A System Level Design Methodology for the Optimization of
Heterogeneous Multiprocessors", M. Schwiegershausen, P. Pirsch -
University of Hannover, Germany
10:30 AM Focus groups: Presentation of results, discussion
12:00 PM Future Directions: Ahmed A. Jerraya
1:00 PM Close of Symposium
LOCATION
The Eighth International Symposium on System Synthesis will be
held at the Gray d'Albion Hotel, Cannes, Cote d'Azur, France.
WWW AND INQUIRIES
All the latest information on ISSS'95, can now be accessed via a
WWW page. The URL for this document is :
http://www.imec.be/isss/isss95.html. For all other inquiries send
email to jerraya@imag.fr or call (+33) 76 57 47 59 during office
hours (GMT+2)
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BOOKS
TITLE: Electronic Packaging, Microelectronics, and Interconnection
Dictionary.
AUTHORS: Charles A. Harper and Martin B. Miller
PUBLISHER: McGraw Hill
1221 Avenue of the Americas
New York, NY 10020
SUMMARY (from book):
Today's rapidly evolving world of electronic packaging and
interconnection is critical to the success of modern
high-performance electronic systems, yet the increasingly
multidisciplinary nature of the field has created a language barrier
that often impedes progress.
This one-of-a-kind dictionary helps professionals and students
understand and correctly use the terminology of both their own specialty
and other disciplines relevant to electronic packaging, microelectronics,
and interconnection. It presents up-to-date entries and clear,
concise definitions for more than 6000 terms and abbreviations, as
well as an extensive section covering acronyms and symbols.
From circuits and communications systems to all types of electronic
subsystems and assemblies, this essential desk reference bridges the
gap between electrical, mechanical, and materials engineering.
1993 copyright. 235 pages. ISBN 0-07-026688-3. $39.95
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TITLE: Electronic Packaging and Interconnection Handbook
AUTHORS: Charles A. Harper
PUBLISHER: McGraw Hill
1221 Avenue of the Americas
New York, NY 10020
SUMMARY (from book):
With today's high-density, high-performance systems, packaging is now
the critical limiting factor to success.
Because of the interdisciplinary nature of packaging, engineers
specializing in materials science, electronics, or mechanical design
are now being asked to have a basic understanding of all three of
these areas. Meeting this growing need, this comprehensive handbook
provides a solid understanding of every aspect of today's packaging
technologies. Written by experts in the field, it provides vital
information on:
o Materials -- how to select the right plastics, ceramics, and metals.
o Thermal Management -- how to minimize the heat in increasingly
dense electronic assemblies.
o Rigid and Flexible Printed Wiring Boards -- design, manufacture,
and application of all types of PWBs.
o Packaging and Interconnecting ICs and Semiconductor Devices -- complete
guidelines including electrical, mechanical, thermal, and materials
parameters.
Plus, packaging of microwave systems...high speed digital systems...
hybrid microelectronics...electro-optical systems...high voltage
systems...and more.
1991 copyright. approx 700 pages. ISBN 0-07-026684-0. $84.50
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TITLE: Physical Architecture of VLSI Systems
AUTHORS: Robert J. Hannemann, Alan D. Kraus, and Michael Pecht
PUBLISHER: John Wiley & Sons, New York
Submitted by L. Fox
SUMMARY: In this book, academic researchers, graduate students, and
practicing mechanical, electrical, and materials engineers will find all
the essentials required to master the packaging and interconnection of
microelectronic components. The book provides thorough coverage of the
interdisciplinary and interfunctional issues that comes with the territory.
Topics covered include thermal control, soldering processes, substrate
technologies, electrical performance, selection of package materials,
reliability, and much more.
The book emphasizes the interaction of electrical, mechanical,
materials, and reliability engineering in the design of modern
electronic products, particularly computers and consumer elec tronics.
It focuses on the underlying principles and technologies that will
remain the basis for electronic design and manufacture through the next
decade.
1994 copyright. 887 pages. ISBN 0-471-53299-1.
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IEEE CPMT INFORMATION
Submitted by Paul Wesling:
The Table of Contents for upcoming/current issues of the IEEE Trans.
on Advanced Packaging can be browsed, to see what topics and papers
are being included. For example, the May issue of this quarterly
journal has a special section of six papers on the topic of
optoelectronics packaging, edited by R. Boudreau, and a second section
of 6 papers on Adhesive Joining Technology in Electronics Manufacturing,
edited by J. Morris. There are other sections on flip-chip packaging,
multichip modules, electrical performance modeling, and other topics in
this issue.
To browse the Table of Contents, access the WEB server at
http://www.ieee.org/pub_preview/cpmtb_toc.html
Each quarter, this location will be updated with the next Table of Contents.
For information on subscribing to this quarterly journal (800 pages/year;
about 100 papers), call IEEE (in the USA tollfree at 1-800-678-IEEE) and
ask for publication 021-1651. Subscriptions are $250/year (non-IEEE
members). You may wish to join IEEE (members get substantial discounts);
if so, request information from IEEE or contact p.wesling@ieee.org for
information.
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