CPMT INFORMATION
CONFERENCES AND WORKSHOPS
SECOND CALL FOR PAPERS
IEEE Multi-Chip Module Conference
MCMC-96
Tutorials: February 5, 1996
Conference: February 6-7, 1996
The Cocoanut Grove, Santa Cruz, CA
Submitted by David Tuckerman
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Sponsored by:
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Circuits and Systems Society
Computer Society
Components, Packaging & Manufacturing Technology Society
Electron Devices Society
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Steering Committee:
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Chair
David B. Tuckerman, nCHIP, Inc.
Technical Program
Paul D. Franzon, North Carolina State University
Local Arrangements
Lisa Pascal, University of California, Santa Cruz
Tutorials
Rui Wang, Intel Corporation
Exhibits
Wayne W. Dai, University of California, Santa Cruz
Past Chair
Robert C. Frye, AT&T Bell Laboratories
Asia Liaison
Teruo Kusaka, NEC Corp., Japan
Far East Liaison
Jun-Dong Cho, Sung Kyun Kwan University, Korea
Europe Liaisons
Bernard Courtois, TIMA/CMP, France
Peter Ivey, University of Sheffield, UK
Others
Sung-Mo (Steve) Kang, University of Illinois
David LaPotin, IBM T.J. Watson Research
James D. Murphy, ARPA
David W. Palmer, Sandia National Labs
King L. Tai, AT&T Bell Laboratories
Jan Vardaman, TechSearch International
Simon Wong, Stanford University
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Conference Highlights:
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Tutorials: In-depth presentation covering relevant MCM related topics.
Technical Sessions: Single track designed to foster interaction among
chip designers, system designers, CAD tool developers, and MCM
technologists.
Invited Talks: Address the latest developments and future trends.
Panel Discussions: Interactive discussions of immediate needs, problem
areas, concerns and innovative solutions.
Exhibits: MCM foundry, Known Good Die technology, MCM design tools,
simulation and layout benchmark posters.
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Technical Topics:
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Design For MCM: system and chip design specifically targeted for MCM
technology -- custom I/O buffers, packaging-driven partition, design
for test, design for manufacturability, design for cost.
MCM Technology for low power systems: minimum capacitance design,
portable electronics.
Analysis: modeling and simulation of electrical and thermal behavior of
MCM structures, noise analysis, delay analysis, performance and cost
driven design.
Applications: innovative uses of MCM technology, system-level optimization.
Technology: novel MCM structures and fabrication methods, integral passive
and active elements, high-frequency and optical interfaces.
Testing: methodology, design and technology for MCM test, Known Good Die,
die- and wafer-level burn-in, boundary scan and built-in self-test
applied to MCMs.
Infrastructure: standards, MCM foundry, university and small company access
to MCM technology.
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For advance program and other information:
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MCMC-96
Attn: Lisa Pascal
Computer Engineering, University of California
Santa Cruz, CA 95064
TEL 408-459-2263
FAX 408-459-4829
lisa@cse.ucsc.edu
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Conference information is also available online on the World-Wide Web
as http:/www.cse.ucsc.edu/~lisa/mcm/mcmc.html
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4th Topical Meeting on Electrical Performance of Electronic Packaging
(EPEP'95)
October 2-4, 1995
Benson Hotel
Portland, Oregon
Sponsored by:
IEEE Microwave Theory and Techniques Society
IEEE Components, Packaging, and Manufacturing Technology Society
EPEP'95 provides a forum for the presentation and discussion of the
latest advances in electrical design, analysis and characterization,
and microwave applications.
Cochairs: A. Deutsch and V.K. Tripathi
Monday, Oct 2, 1995
Session 1: System Issues in Package Design
Session 2: High Performance Microprocessor Packaging and Interconnects
Session 3: Simultaneous Switching Noise
Session 4: Decoupling Capacitors
Session 5: One-on-One Open Forum (Poster)
Tuesday, Oct 3, 1995
Session 6: Measurement Techniques
Session 7: Optical/Electrical Communication Links
Session 8: Wireless Communications
Session 9: Microwave Packaging
Wednesday, Oct 4, 1995
Session 10: Simulation
Session 11: Modeling I
Session 12: Modeling II
REGISTRATION INFORMATION
Engineering Professional Development
Box 9 Harvill Building, Room 235
Second and Olive Streets
Tucson, Arizona 85721-0076
Tel: (520) 621-3054
Fax: (520) 621-1443
Email: baltes@bigdog.engr.arizona.edu
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Advanced Technology Workshop
March 2-6, 1996
Chateau Elan
Braselton, GA 30517
(50 miles northeast of Atlanta).
Submitted by Debra Kelley
This workshop precedes the 2nd International Symposium on Advanced Packaging
Materials: Processing, Properties and Interfaces (see ITEM 2.4)
For more information contact ISHM, 703-758-1060.
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2nd International Symposium on Advanced Packaging Materials:
Processing, Properties and Interfaces
March 6-8, 1996,
Atlanta, GA.
Submitted by Debra Kelley
Sponsored by:
ISHM - The Microelectronics Society
IEEE Component Packaging & Manufacturing Technology
Georgia Institute of Technology.
This symposium will be devoted to the advances made in electronic
packaging materials. The symposium attendees will be comprised of
researchers, developers, producers and users of materials for single
and multichip packages, interconnections, substrates, microwave
applications, optoelectronic packages and display panels. The
following technical areas will be emphasized:
Chip-to-Substrate Interconnection Materials
DCA & BGA Materials and Processes
Ceramic Packaging Materials
Polymer Dielectrics
Plastic Package & Encapsulation Materials
Thermal Management Materials
Microwave Packaging Materials
Optoelectronic Packaging Materials
Display Materials
Advanced Organic Boards
Integrated Passive Compoent Materials
Large Format Substrates
Low Cost Packaging Materials
High Circuit Density Interconnect Materials
Each session will consist of a keynote speaker and 3 papers on the
recent advances made in the field.
To submit an abstract send an original and 1 copy of your extended
abstract by 9/1/95. Abstracts should be a minimum of 1 page (200
words). no formal, full length paper will be required. Send to
ISHM Technical Program Development, 1850 Centennial Park Dr., Suite 105,
Reston, VA 22091. Phone: 703-758-1060 FAX: 703-758-1066
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ELECTRONICS MANUFACTURE & ASSEMBLY SEMINAR
A joint Salford University/Loughborough University seminar
25 October 1995
Salford, UK
Submitted by: D. Whalley
Salford University and Loughborough University are organising a
joint seminar to industry on electronics packaging issues. The
seminar which will be held at The Research and Graduate College,
University of Salford, will bring together participants from
industry and academic groups working on EPSRC funded projects in
the area of electronics manufacture and assembly. Grant holders
on the EPSRC's Electronic Product Design and Manufacture (EPDM)
Initiative, and other University research groups will also be
participating in the seminar.
The primary objective of the one-day seminar is to provide an
industrial focus for academic research in electronics manufacture
and assembly, and to increase the level of interaction between
industrial and academic R & D groups. The seminar will also
provide further co-ordination of the work of the academic groups,
and promote dissemination and exploitation of research results.
The seminar will be addressed by David Topham, the Coordinator
of EPSRC's EPDM Initiative, and a keynote presentation on
"Environmental Challenges facing the UK Electronics Industry",
will be given by Dr Colin Lea of The National Physical
Laboratory, Teddington. The main technical session will consist
of three 20-minute presentations on: Applications of physics of
failure to electronics interconnect reliability; Industrial
applications of Laser Soldering; and Process modelling of Solder
Paste Printing. This will then be followed by short presentations
by each academic group on their research activities. Poster
session and demonstrations will be used for further dissemination
of results of other work.
The seminar is being sponsored by the Design Manufacture and
Marketing Research Institute of the University of Salford, and
is supported by the CDP/EPSRC Group, the Royal Academy of
Engineering and the SMART Group. The ITIC and the NPL Industry
Club members, and representatives of other Electronics
Manufacturing Industry and Professional groups are also being
invited.
For further information please contact:
Dr Ndy Ekere CEng MIEE
Aeronautical, Mechanical and Manufacturing Engineering Department
University of Salford, SALFORD M5 4WT
Telephone: 0161 745 5000 Ext 3128
Fax: 0161 745 5575
Email: N.N.Ekere@Aeromech.salford.ac.uk
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Second European Surface Mount Conference
13-14 November 1996
Old Ship Hotel
Brighton UK
Submitted by: Peter Swanson
Following on from the tremendous success of the European Surface Mount
Conference in Brighton in November 1994, a second event is planned.
Again it will be organised by the SMART Group in collaboration with other
bodies in the electronics manufacturing sector. The intention is to
establish a regular biennial series of conferences.
We want to hear from you
-------------------------
You are invited to submit a 200-300 word abstract of a paper on a
topic suitable for inclusion in one of the 4 Sessions:
Components, including PCBs, substrate technologies, solderable finishes,
etc.
Advanced technologies, including flip chip, COB, MCMs, TAB, etc.
Quality, including reliability assessment, yields, etc.
Management issues, including environmental, recycling, safety, etc.
Your proposed paper should be of original or unpublished work, case
histories, research or discoveries. IT MUST BE NON-COMMERCIAL and
preferably user-orientated.
DEADLINES
Abstracts are due: 8 December 1995
Authors will be notified of their selection in January 1996
Full paper in its final form required: 31 July 1996
PAPER SUBMISSION
200-300 word abstract plus author's details to:
Colin Lea
National Physical Laboratory
Teddington
Middlesex TW11 0LW
UK
fax: +44 (0)181-943 2989
WORKSHOPS (Share your knowledge}
The event in November 1996 will include a series of workshops. Expressions
of interest are sought from potential instructors for 3-hour workshops.
Encouragement is given to proposals focusing on applications and
problem-solving, illustrated by case studies.
Please include in your proposal:
- workshop objectives (50 words max)
- workshop description (300 words max)
- instructor's resum=82 (200 words max)
- who should attend (50 words max)
Proposal Deadline: 8 December 1995
Workshop proposals and instructor's details to:
Colin Lea
National Physical Laboratory
Teddington
Middlesex TW11 0LW
UK
fax: +44 (0)181-943 2989
Exhibition (A not-to-be-missed event)
A compact, low-cost exhibition will be held in conjunction with the
conference. Ask for an exhibitor's pack including details of costs and
how to make a reservation. Space will be allocated strictly on a first
come basis.
For exhibitor information contact
Tony Gordon
The SMART Group
fax: +44 (0)1494-473 975
e-mail: smart@smtuk.demon.co.uk
The SMART Group is a not-for-profit trade association. SMART is for the
advancement of surface mount a related technologies. It is the largest
association of its kind in Europe.
Posted by:
Peter Swanson, Chairman, The SMART Group
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ADVANCE PROGRAM
VLSI Packaging Workshop: Spotlight BGA
October 16-18, 1995
Hyatt Regency, Monterey, California
Submitted by Bill Hamburgen
Program Committee Chair - 1995 VLSI Packaging Workshop
The VLSI Packaging Workshop, now in its 15th year, is a program of the
IEEE-Components, Packaging Manufacturing Technology Society's Technical
Committee on Packaging (TC-6). Co-sponsorship is provided by the National
Institute of Standards and Technology.
Workshop participants represent a broad international spectrum of engineering
disciplines from commerce and academia. To ensure wide representation and
foster in-depth discussion and technical interaction, attendance is limited.
To encourage a frank exchange on up-to-the-minute findings, there are no
published proceedings, and cameras and tape recorders are not permitted.
A copy of the Extended Abstracts will be available to Workshop Participants.
This year, the Workshop focus will be BGA and chip-sized packaging, though
as the attached advance program shows, other important packaging topics are
included. There will be 25 presentations in 5 plenary sessions plus a
session for recent results.
Program Chair General Chair
Bill Hamburgen Elaine Pope
Digital Equipment Corporation Intel Corporation
250 University Avenue 5000 W. Chandler Blvd.
Palo Alto, CA 94301 Chandler, AZ 85226 MS: CH5-137
Phone: (415) 617-3329 Phone: (602) 554-5368
FAX: (415) 617-3374 or -3375 FAX: (602) 554-7945
billh@pa.dec.com d_elaine_pope@ccm.hf.intel.com
For information on vendor demonstration tables and workshop registration,
please contact:
Engineering Professional Development, Box 9 - Harvill Building - Room 235
Second and Olive Streets Phone: (602) 621-3054
University of Arizona FAX: (602) 621-1443
Tucson, AZ 85721-0076 baltes@bigdog.engr.arizona.edu
Up-to-date workshop information can be found on the World Wide Web at:
http://www.research.digital.com/wrl/projects/VLSI_Pkg_Workshop/main.html
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REGISTRATION:
You are encouraged to submit the Advance Registration Form as soon as
possible. The registration fee is $375 for IEEE Members and for speakers
and session chairs, $495 for non-members, $250 for a one-day registration
and $200 for students. The fee covers all breakfast coffee and rolls,
refreshment breaks, two luncheons, Monday evening reception, Tuesday evening
California Beach Party and Bar-B-Que, and a copy of the Extended Abstracts.
Payment is due with your registration form (checks may be made payable to
"THE UNIVERSITY OF ARIZONA" or pay by Visa or MasterCard). Refunds will be
made for cancellations received on or before October 6, 1995.
The Workshop Registration Desk in the hotel Conference Center will be open
from 5-8 p.m. on Sunday, October 15th, and at 7:00 a.m. Monday, the 16th.
The Keynote Session begins at 9:00 a.m. sharp.
ACCOMMODATIONS:
The Hyatt Regency Monterey is the headquarters hotel for the Workshop
and all Workshop sessions will be held there. A block of rooms at
special Workshop rates has been reserved for participants and attendees.
Workshop room rates are $119, including tax, for single and double occupancy.
Check-in time is 3:00 p.m. and check-out is 12:00 noon. Room reservations
should be made directly with the hotel at (408) 372-1234, FAX (408) 375-3960.
When making reservations, be sure to identify yourself as attending the
IEEE VLSI Packaging Workshop to receive the special rate. Reservations
must be made September 14, 1995 to guarantee this rate. After this time,
reservations will be accepted on a space available basis only.
Special guest services include six championship tennis courts, two sparkling
swimming pools, health club, whirlpools and parcourse. The hotel is within
minutes of the Monterey Bay Aquarium, Fisherman's Wharf, Cannery Row, Pebble
Beach, 17 Mile Drive and the shops of Carmel.
LOCATION AND TRANSPORTATION:
The Hyatt Regency Monterey is located at One Old Golf Course Road, Monterey,
California 93940, Phone: (408) 372-1234, FAX: (408) 375-3960, five minutes
from the Monterey Peninsula Airport. Approximate fare for a taxi is $7.00
for one person, one way. Five major rental car companies are available in
the terminal.
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MONDAY, OCTOBER 16 - 9:00 a.m.
Welcome to the Workshop
Elaine Pope - Intel, General Chair
Bill Hamburgen - Digital Equipment, Program Chair
Keynote Address: "A System Approach to Assembly and Packaging Cost" -
Robert Werner - Sematech
Session I. High Performance BGA: Session Chairs: Kanji Otsuka - Meisei
University, and Bill Schmidt - Silicon Graphics
"High Performance BGA" - E. Hagimoto, H. Nakajima, K. Terajima,
K. Shibuya, H. Fukunishi, T. Handa and S. Takahashi - NEC Corp.
"Advanced Ball Bond Processing for BGA Packaging" - V. P. Jaecklin,
S. Arsalane, D. von Flue, H. Egger and Z. Stossel - ESEC SA
"Ball Grid Array Package Design Optimization for High Performance
Microprocessors" - Joseph Adam & Sharad Shah - Digital Equipment
"High-Performance Cavity P-BGA Package" - Hiroshi Seki, Tomoaki
Hashimoto, Masatoshi Yasunaga, Jun Shibata, Akiyoshi Sawai,
Yoshikazu Narutaki, Ken Yamamura, Taketoshi Shikano,
Mitsuaki Hisahara, Hideki Fukunaga - Mitsubishi Electric Corp.
"High Performance Organic Single Chip Package" - Bill Petefish -
W.L. Gore and Associates, Inc.
Luncheon talk: "Why you should care about the Internet even though it has
made the cover of Time Magazine" - Brian Reid - Digital Equipment Corp.
MONDAY, OCTOBER 16 - 2:00 p.m.
Session II. Modeling of BGA Performance: Session Chairs: Michael Gaynes -
IBM, and John Prince - University of Arizona
"Characterization of Angled Bonding Wires for High Frequency Inte-
grated Circuits" - Sang-Ki Yun and Hai-Young Lee - Ajou University
"RF-Investigation of the Electrical Parameters of the Embedded
Chip Structure" - A. Owzar, K. Buschick, O. Ehrmann and
M. Kasper - Technical University Berlin
"Finite Element Analysis of Overmolded Plastic BGA Package" -
Teo Yong Chua, Tay Nam Beng, Lim Thiam Beng, Tan Geok Leong, Navin
Bhandarkar and Kishore Chakravorty - Institute of Microelectronics
"Compact Inductance Matrix for delta-I Noise Simulation" -
Atsushi Nakamura, Tatsuya Nagata, Hiroya Shimizu,
Hideshi Fukumoto and Akihito Yokomori - Hitachi, Ltd.
"BZT Thin Film Capacitor for MCM" - Nobuo Kamehara, Mineharu Tsukada,
Jeffery Cross and Kazuaki Kurihara - Fujitsu Laboratories, Ltd.
MONDAY, OCTOBER 16 - 5:30 p.m.: Hosted reception
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TUESDAY, OCTOBER 17 - 9:00 a.m.
Session III. BGA Package to Board Attach: Session Chairs: Nobuo Kamehara -
Fujitsu Laboratories, and Dennis Olsen - Motorola
"Ceramic Column Grid Array Package for IBM PowerPC 620
Microprocessor" - S. K. Ray, H. Quinones, M. Carlson and
H. V. Mahaney - IBM Corp.
"Analysis of Reliability Conditions for Interconnection by
Anisotropic Conductive Adhesion" - Kanji Otsuka -
Meisei University
"Performance Results for Epoxy Attached, 10 Watt, Flipped Chips" -
Justin Bolger, Merix Corp. and Wayne Johnson, Auburn University
"Flip Chip Attach with Isotropic Electrically Conductive Adhesive" -
Michael A. Gaynes, Russell H. Lewis, Ravi Saref,
and Judith Roldan - IBM Corp.
"Low Cost Flip Chip Consortium" -
Luu T. Nguyen - National Semiconductor Corp.
TUESDAY, OCTOBER 17 - 2:00 p.m.
Session IV. Reliability of BGA Packages: Session Chairs: Eric Beyne - IMEC,
and Atsushi Nakamura - Hitachi
"Development of a Quick, Easy-to-use Graphical Predictor of
Package/Module Interconnect Reliability" -
Ray Iannuzzelli - Digital Equipment Corp.
"Surface Insulation Resistance Testing of a 313 PBGA" -
Joyce Hyde - Digital Equipment Corp.
"BGA and CSP Application of Flip Chip Interconnection" -
Yoichi Hiruta, Kazuhide Doi, Naohiko Hirano, Takashi Okada
and Toshio Sudo - Toshiba Corp.
"Technology and Reliability Assessment of 313 I/O OMPAC Style PBGA"
Lidia Lee, Joyce Hyde, Tom Solon and Skip Gates -
Digital Equipment Corp.
"Solderability and Reliability Study of High-Performance PBGA
and CBGA" - Katsumi Kaizu and Tohru Kishimoto - NTT Corp.
TUESDAY, OCTOBER 17 - 6:00 p.m.: California Beach Party and Bar-B-Que
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WEDNESDAY, OCTOBER 18 - 8:30 a.m.
Session V. Novel BGA Packages and Processes: Session Chairs: Justin Bolger -
Merix, and Hiroshi Shibata - Mitsubishi Electric
"LFBGA Lead Frame for BGA Package" - Yoshinori Ota, Tomonori
Matsuura, Toshiya Migitaka, Shigeki Kawano, Syuubou Taya, Shuji
Sagara and Yasuhiko Nishikubo - Dai Nippon Printing Co., Ltd.
"The Stud Grid Array, A Low Cost Solution for Packaging and
Assembling High Pin Count Devices" - Eric Beyne, F. Christiaens
and J. Roggen - IMEC, and J. Van Puymbroeck, Ann Dumoulin,
Luc Boone and M. Heerman - Siemens LPT
"Solder Transfer Technique - A Possibility for Performing
Bumps for Flip Chip Applications and BGA's" -
J. Wolf - Fraunhofer Institute and
M. Topper - Technical University Berlin
"Flip Chip Interconnection on Flexible Circuit with Laser" -
G. Azdasht - Technical University Berlin and P. Kasulke,
E. Zakel and H. Reichl - Fraunhofer Institute
"A New Solder Joint Technology for Ceramic BGA" - Shin Matsuda,
Nobuyuki Itoh and Masami Terasawa - Kyocera Corp.
Session VI. Recent Results Session
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--------- Registration Form: Detach and Return by October 6, 1995 -----------
Please attach business card or fill in:
Dr/Mr/Ms ____________________________ Position/Title ______________________
Company/Institution _______________________________________________________
Mailing Address ___________________________________________________________
City _____________________ State/Country __________________ ZIP _________
Phone _________________ FAX ___________________ Email ___________________
Please describe involvement with chip packaging (required):
___________________________________________________________________________
___________________________________________________________________________
Advance registration for all Sessions, copy of the Extended Abstracts, two
luncheons, Monday evening reception, and Tuesday Beach Party and Bar-B-Que:
NO REGISTRATION WITHOUT PAYMENT
IEEE Members and Speakers...........$375
Non-Members......................... 495
One-Day Registration................ 250
Student Registration................ 200
__ __ __
Please check: | | Speaker | | Session Chair | | Committee
`--' `--' `--'
Make checks payable in U.S. dollars to: THE UNIVERSITY of ARIZONA
For those wishing to pay by credit cards: (Master Card or Visa only):
Visa/MasterCard # _____________________________________ Exp. __________
Signature _____________________________________________ Date __________
I have the following special needs/requirements:
___________________________________________________________________________
___________________________________________________________________________
Send completed registration form to:
Engineering Professional Development
Box 9, Harvill Building, Room 235
Second and Olive Streets
University of Arizona
Tucson, AZ 85721-0076
Phone: (520) 621-3054
FAX: (520) 621-1443
Email: baltes@bigdog.engr.arizona.edu
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DIRECTIONS TO THE HYATT HOTEL IN MONTEREY CALIFORNIA:
Hyatt Regency Monterey
One Old Golf Course Road
Monterey, California 93940
Phone: (408) 372-1234
FAX: (408) 375-3960
Traveling on Highway 101 South:
- Take highway 101 South, turn onto California Route 156 West
- Merge with California Route 1 South
- Take first Monterey exit: "Pacific Grove, Del Monte Avenue"
- Continue straight after exiting, you will be on Del Monte Avenue
- Continue on Del Monte Avenue to third traffic light
- At this traffic light, turn left onto Sloat
- Hyatt Hotel driveway is at end of Sloat
Traveling on Highway 1 North:
- Take "Aguajito, Mark Thomas" exit
- Continue straight ahead through first light
- At second light, turn right up the hill to the Hyatt Hotel
Traveling from Los Angeles on Highway 101 North:
- From highway 101 North, take California Route 68 West (Salinas exit)
- Follow California Route 68 to the Monterey Airport
- At the airport, turn right toward the terminal (Olmstead Road)
- Take the next left onto Garden Road
- Continue to the end of Garden Road. At the traffic light, take a
left onto Mark Thomas.
- At the next light take a left up the hill to the Hyatt Hotel
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Seventeenth IEEE International
Electronics Manufacturing Technology
Symposium
October 2-4, 1995 Austin, Texas USA
Submitted by: Terry Chappell
ADVANCE PROGRAM
Theme: Manufacturing Technologies--Present and Future
Sponsored by:
Components, Packaging, and Manufacturing Technology Society
of the IEEE and
Electronic Industries Association
* * * * * Sessions * * * * *
Flip Chip Developments
Manufacturing Management
Modeling, Diagnostics, and Control of Semiconductor Manufacturing
High Density Interconnects: Manufacturing Substrates, Modules,
& 3D Packages
Product Integrity
Advanced Scheduling Methodologies for Semiconductors and Controllers
Intelligent Manufacturing Neural Networks
Environmentally Conscious Mfg.
Semiconductor Minifabs
Fine Pitch Bonding, Ultra Small Packages
Soldering
Modeling & Statistical Methods
Design for Manufacturing
Ball Grid Array Packages
* * * * * Exhibits Open All Day Tuesday * * * * *
Monday Morning, October 2
************************
Flip Chip Developments
Session M1A (8:30 - 11:15)
************************
Chair: Thomas Goodman, TechSearch Int'l
Co-Chair: Greer Person, LSI Logic
Organizations that learn how to design and manufacture direct flip chip
attach to substrates can make major advances in electronic packaging.
Great benefits can be gained in performance, quality, cost, size, and weight.
This session will focus on the material, process, and
reliability issues of flip chip technologies.
Solder Bumping Through Super Solder
Toshiaki Amano, Yasuhisa Kaga, Masanao Kohno*, Yuichi Obara#
Furukawa Electric, *Harima Chemicals,
#Super Solder Technologies, Japan
Underfill Flow as Viscous Flow Between Parallel Plates Driven by
Capillary Action
Matthew Schwiebert
Hewlett Packard
Study of Void Formation in Flip-Chip Solder Bumps - Part I
Lakhi Goenka, Achyuta Achari
Ford Motor
Fluxless Flip-Chip Attachment Techniques Using the Au/Sn Metallurgy
Christine Kallmayer, Joachim Kloeser, Erik Jung,
Elke Zakel, Herbert Reichl
Technical University of Berlin
Flip Chip Process Development Techniques Using A Modified Research &
Development Aligner Bonder
Gretchen Adema, Sundeep Nangalia, Nick Koopman, Michael Schneider*,
Vicki Saba*
MCNC, *Research Devices
************************
Manufacturing Management
Session M1B (8:30 - 11:45)
************************
Chair: Mike Cassidy, AT&T
Co-Chair: Wyck Seelig, AT&T Bell Labs
Leaders from industry and academia will present the latest thoughts on
managing an electronics enterprise amidst rising expectations by
customers, employees and owners. Managing for a changing future,
reducing cycle-time, increasing agility, modelling the supply chain and costs
of assembly and inspection, fostering ownership and teaming will
all be discussed.
Managing for a Future
Michael Kelly
Georgia Institute of Technology
Estimating Tools to Support Multi-Path Agility in Electronics Manufacturing
Robert Graves, Ashok Agrawal, Kathy Haberle
Rensselaer Polytechnic Institute
A Framework for Supply Chain Management in Semiconductor Manufacturing
Industry
Irfan Ovacik, Willie Weng
i2 Technologies
Modeling the Cost of Assembly and Inspection
Daren Dance, Thomas DiFloria*, David W. Jimenez#
SEMATECH, *Texas Instr, # Wright Williams & Kelly
Manufacturing Ownership Through Process Re-Engineering
Stobaugh
How TOC and TPM Work Together to Build the Quality Tool Box of SDWTs
Ed Rose, Ray Odom, Jim Hinchman, Randy Dunbar
Harris Semiconductor
************************
Modeling, Diagnostics, and Control of Semiconductor Manufacturing
Session M1C (8:30 - 11:45)
************************
Chair: Albert Hu, San Jose State Univ.
The development of equipment modeling tools have enabled improved ability to
diagnose and control the semiconductor manufacturing process. This permits
the improved control of the actual process to achieve higher
yields and improved process control.
Run by Run (Generalized SPC) Control of
Semiconductor Processes on the Production Floor
James Boyd, Max Banan
Delco Electronics
Correlation Between Yield and Waiting Time: A Quantitative Study
Krishna Srinivasan, Raka Sandell, Steven Brown
SEMATECH
Contamination Control Using Produduction Test Data
Young-Jun Kwon, Duncan M.H. Walker
Texas A&M University
Reducing Cycle Time Through Programmable Multichip Modules
Jeffrey Banker, Robert Miller
Pico Systems
Run by Run Control of Chemical Mechanical Polishing
Duane Boning1, Arnon Hurwitz(2), James Moyne(3), William Moyne1,
Scott Shellman(4), Taber Smith(1), John Taylor(5), Roland Telfeyan(3)
(1)MIT, (2)SEMATECH, (3)U. of Mi, (4)BYU, (5)Compugenesis
Metrology Control for an Advanced 200 mm Sub-Micron Wafer Fab
Syed Haider, Faa Ching Wang, Victor Hegemann, John Capps, Ron Price
Texas Instruments
* * * * * IEMT Luncheon & Keynote Address * * * * *
(12:00 - 1:30)
In Pursuit of Excellence--the Deming Prize Story
Michael Cassidy
Quality Director, AT&T Power Systems
Luncheon is included in your registration fee. You may purchase additional
tickets for guests in advance or at the registration table for $25 each.
Monday Afternoon, October 2
************************
High Density Interconnects:
Manufacturing Substrates, Modules, & 3D Packages
Session M2A (1:45 - 5:30)
************************
Chair: Tom Chung, MCC
Co-Chair: Robert Crowley, TechSearch, Int'l
The increasing need for greater interconnect density has exerted pressure on
electronics packaging. This session examines recent progress in high density
interconnect technology.
High-Density Build-Up Wiring Boards Using Conventional Printed Wiring
Board Process
Satoshi Itaya, Hideki Miyazawa, Etsuji Morimoto, Yoshiro Takahashi,
Yutaka Uno, Kei Nakakuki, Yasuo Iguchi
Oki Electric
Electrical and Thermo-Mechanical Studies of MCM-D Interconnect Structure
Fang-Lin Chao, Ruey-Beei Wu*, Michael Pecht#
Da-Yeh Institute of Technology, *National Taiwan Univ.,
#Univ. of Maryland
Cost Effective Micro Via Generation by a TEA CO2 Laser for High Density
Interconnection Technology
Bo Gu
Lumonics
COB and COC for Low Cost and High Density Package
Georges Rochat, Don Styblo
Valtronic USA
Electrical Performance Analysis of a Three-Dimensional Package
Seung-Ho Ahn, Kyung-Sun Lee, Ekkehard Miersch
Samsung Electronics
Laser Micromachining of Through-Via Interconects in Active Die for 3-D
Multichip Module
Dahwey Chu, W. Doyle Miller
Sandia National Labs
Dual Chip Memory Package
Young-Do Kweon
Samsung Electronics
************************
Product Integrity
Session M2B (1:45 - 5:30)
************************
Chair: Elaine Pope, Intel
Co-Chair: Paul Wesling, Tandem Computers
The integrity of the product that comes from manufacturing is becoming a key
measure of customer acceptance. This session examines product reliability
and integrity issues.
Product Integrity Assessment Using Fatigue Synthesis for Avionics
Programs
Mostafa Rassaian, Doug Pietila
Boeing
Snap Cure Die Attach Reliability
David Galloway, Michael Grosse*, My N. Nguyen*
Motorola and Johnson Matthey Electronics*
Reliability of Soldered Silicon Devices on Copper Alloys
Achyuta Achari, Wells Green
Ford Motor
On Temperature ALT at the PBA Level
C.R. Yang, K.O./ Lee, J.T. Kim
ETRI
Plasma Process Control with Optical Emission Spectroscopy
Pamela Ward
Sandia National Labs
Inspection of Power-Plane Short Fault with Irregular and Perforated Shape
Ruey-Beei Wu, Fang-Lin Chao*
National Taiwan Univ., *Da-Yeh Inst. of Technology
Laser Ablation Forward Deposition of Metal Lines for Electrical
Interconnects Repair
Karim Tatah, Akira Fukumoto, Carl V. Thompson*
Panasonic Technologies, *MIT
************************
Advanced Scheduling Methodologies for Semiconductors and Controllers
Session M2C (1:45 - 5:00)
************************
Chair: Jim Steele, Motorola
Co-Chair: Dennis Olsen, Motorola
Semiconductor wafer and controller fabrication are extremely complex
manufacturing processes. Development of scheduling methodologies has
resulted in significantly improving WIP and machine utilization along
with shorter cycle times and more predictable on-time delivery.
Manufacturing Systems Analysis: Electronic Controller Applications for
Chrysler Electronics
John Evans, Scott Thomason, Scott Zeigler, Dawn Lambert, Larry Goins,
Phil Farrington*
Chrysler Electronics, *Univ. of Alabama - Huntsville
New Methodology of Dynamic Lot Dispatching Required Turn Rate
Wen-Cheng Chin, Jiann-Kwang Wang, Kuo-Cheng Lin, Seng-Rong Huang
Taiwan Semiconductor
Scheduling of Semiconductor Manufacturing Plants
David Sohl, P. R. Kumar
University of Illinois
Iterative Capacity Allocation and Production Flow Estimation for
Semiconductor Fabrication
Shi-Chung Chang, Loo-Hay Lee, Lee-Sing Pang, Thomas W.Y. Chen*,
Yi-Chen Weng*, Huei-Der Chiang*, David W.H. Dai*
Nat'l Taiwan Univ. and *Taiwan Semiconductor
Decomposition Algorithms for Scheduling Semiconductor Testing Facilities
Ebru Demirkol, Irfan M. Ovacik*, Reha Uzsoy
Purdue University, *i2 Technologies
Production Improvements Using a Forward Scheduler
Robert Juba
IBM Microelectronics
Tuesday Morning, October 3
************************
Intelligent Manufacturing Neural Networks
Sesson T1A (8:30 - 11:15)
************************
Chair: Henry Law AT&T Bell Labs
Co-Chair: Kam Yeung AT&T Bell Labs
Applying neural nets to manufacturing control has started to move from the
laboratory to the production floor. This session looks at the application of
neural nets to the shop floor.
Designing Response Surface Model based Run by Run Controllers: A New
Approach
John Baras, Nital S. Patel
Univ. of Maryland
Use of Neural Network in Modeling Relation between Exposure Energy and
Pattern Dimensions in Photolithography Process
G. Cardarelli, M. Palumbo, P.M. Pelagagge
Univ. of L'Aquila, Italy
Modeling and Recipe Generation of Plasma Etching Process using Neural
Networks and Genetic Algorithm
Taek-Beom Koh, Sang-Yeob Cha, Kwang-Bang Woo, D.S. Moon*, H.S. Chang*
Yonsei University and *Samsung Electronics
Real-Time Diagnosis of Semiconductor Manufacturing Equipment Using Neural
Networks
Byungwhan Kim, Gary S. May
Georgia Institute of Technology
Automated Inspection of Solder Joints - A Neural Network Approach
Vijay Sankaran, Brent Chartrand, Don L. Millard, Mark J. Embrechts,
Russell P. Kraft
Rensselaer Polytechnic Institute
************************
Environmentally Conscious Manafacturing
Session T1B (8:30 - 11:15)
************************
Chair: Larry Felton, RPI
Co-Chair: Tsung-Yu Pan, Ford Motor
The concern for the environment is taking a greater part of the manufacturing
professional effort. This session addresses some of the issues and solutions
to make manufacturing more "user-friendly".
Lead-Free Interconnect Materials for the Electronic Industry
Duane Napp
National Center for Manufacturing Sciences
Solderability Testing of Alternate Component Termination Materials with
Lead-Free Solder Alloys
Paul Conway, David C. Whalley, Mehrdad R. Kalantary
Loughborough Univ. of Technology, UK
Measurements of Thermal Conductivity and Specific Heat of Lead-Free Solder
John Lloyd, Chao Zhang, H. Leong Tan, Dongkai Shangguan*,
Achyuta Achari*
Michigan State Univ. and *Ford Motor
Experimental Thermomechanical Hysteresis and Fatigue of Pb-Free Solder
Alloys with Reference to the Sn-Pb Eutectic
C.H. Raeder, L.E. Felton, R.W. Messler, L.F. Coffin
Rensselaer Polytechnic Institute
Ozone Safe Solvents for Electronics Manufacturing
Dwight Williams, John A. Moore
Dow Corning
************************
Semiconductor Minifabs: Concepts and Implementation Issues I
Session T1C (8:30 - 11:45)
************************
Chair: William Barnett, Fluor-Daniels
Co-Chair: L. Ken Keys, Louisiana State U.
This is Part 1 of a two part session that looks at manufacturing issues
in the semiconductor industry. The presentations range from management
of manufacturing flow to analysis of bottleneck equipment to select areas
for improvement.
Total Contamination Control: The Minienvironment Era
Salem Abuzeid
Asyst Technologies
Implementation of Robotically-Loaded Mini-Environments in an ASIC Production
Facility
Robert Epifano
SEMATECH
The Experience of Lead Users in the Adoption of Mini-Environment
Technology
Michael A. Rappa
MIT
Design of Future Single Wafer Logic Fabs
Paul Castrucci
P.C.&A.
Impact of Mini-environments on Facilities Cost
William J. Barnett, Raymond Schneider
Fluor-Daniels
Utilizing Production Data to Increase Factory Capacity
John Konopka, Walt Trybula
SEMATECH
Modular/Minifab Design and Construction - An Unusual Approach
Dave Gunderson
Fluor Daniel
Tuesday Afternoon, October 3
************************
Fine Pitch Bonding, Ultra Small Packages, and Assembly
Session T2A (1:45 - 5:30)
************************
Chair: Mike McShane, Motorola
Co-Chair: Michail Salijoty, Solectron
Improved methods for manufacturing with fine pitch packages and demands
for smaller products continue to offer challenges. This session addresses
developments in fine pitch bonding, new ultra small packages, and assembly
methods.
Development of Ultra-Fine Pitch Ball Bonding Technology
Yasuhide Ohno, Kouhei Tatsumi, Osamu Kitamura*, Takashi Katsumata#,
Masayuki Furusawa#
Nippon Steel, *Nippon Micrometal, #Kulicke & Soffa
Fine Pitch Thermosonic Wire Bonding: Analysis of State-of-the-Art
Manufacturing Capability
Daniel Cavasin
Motorola
Development of 0.5mm Thick Small Outline Packages
Young-Jae Song
Samsung Electronics
A Novel Structure to Realize Non-Cracking Plastic Package During Reflow
Soldering Process--Development of CSS (Chip Side Support) Package
Tsutomu Nakazawa, Yumi Inoue, Kanako Sawada, Toshio Sudo
Toshiba
Distributed Control of Hot Bar Thermode in Fine Pitch SMT
Vitor Skormin, Keumsaeng Park
Binghamton Univ.
Laser Diode-Based Soldering System with Vision Capabilities
Paul Laferriere, Akira Fukumoto
Panasonic Technologies
Nitrogen Reflow Ovens: The Effect Exit Temperature Has On Benzotriazole
Coated Copper Boards
S. Gutierrez, D. Saxton, R. Schluter, P. Thune
IBM P. C. Company
************************
Soldering
Session T2B (1:45 - 5:30)
************************
Chair: Spike Narayan, IBM
Co-Chair: Achyuta Achari, Ford Motor
With the concern for defect-free assembly, soldering is an extremely
important consideration for the manufacturing professional. This session
looks at the improvements in the soldering process and materials.
Towards a Standard for DSC Measurement of Solder Paste Products
M.R. Kalantary, P.P. Conway, F. Sarvar, D.J. Williams, M.A.S. Main*
Loughborough Univ. of Technology and *BNR, U.K.
Flux Activity Evaluation Using the Wetting Balance
C-Y. Huang, K. Srihari, A.J. McLenaghan*, G.R. Westby*
State Univ. of New York, *Universal Instruments
Measurement of Solder Paste Component Retention Properties
Sunil Thomas, K. Srihari, A. James McLenaghan*, G.R. Westby*
State Univ. of New York, *Universal Instruments
Assembly Yield Modeling of Fine Pitch Devices for Mass Reflow Application
Hakan Ugur, James Adriance, George Westby
Universal Instruments
A Method toward Defect-Free and Reliable Solder Joints in Reflow Soldering
D.J. Xie, Y.C. Chan, J.K.L. Lai
City University of Hong Kong
Soldering on Gold Plated Substrates - Solder Joint Reliability and Integrity
of Surface Mount Components
Jaya Ganasan
Crystalaid Manufacture, Australia
Properties of Thin Layers of Sn62Pb36Ag2
Gunter Grossman
ETH, Switzerland
************************
Modeling & Statistical Methods
Session T2C (1:45 - 5:00)
************************
Chair: John Konopka, SEMATECH
Co-Chair: Walt Trybula, SEMATECH
Understanding and analyzing the process is the first step toward improving
it. Organizations that learn how to apply these tools gain a competitive
advantage. This session focuses on means for analyzing the factory and
on applying statistical methods to control it.
Effective Modeling of Factory Throughput Times
N. Srivatsan, Karl Kempf
Intel
Alternative Facility Layouts for Semiconductor Wafer Fabrication
Facilities
Rieko Hase, Christos G. Takoudis, Reha Uzsoy
Purdue University
Reusable Modeling Capabilities for Simulating High Volume Electronics
Manufacturing Systems
Phillip Farrington, James J. Swain, John L. Evans*,
Sherri L. Messimer, John S. Rogers, and Bernard J. Schroer
Univ. of Alabama in Huntsville, *Chrysler Electronics
Model-Based Product Quantity Control
Venkatakrishnan Ramakrishnan, Duncan M.H. Walker
Texas A&M University
A Robust Metric for Measuring Within-Wafer Uniformity
Joseph Davis, R.S. Gyurcsik, J.C. Lu, J. Hughes-Oliver, D. Nychka
North Carolina State Univ.
Gage Repeatability and Reproducibility Study for Solder Paste Height
Using a Laser Scanning Microscope
Ken Jones, Jr., William S. Messina, Leslie G. Willey
Chrysler Electronics
Wednesday Morning, October 4
************************
Ball Grid Array Packages: Fabrication and Manufacturing
Session W1A (8:30 - 11:45)
************************
Chair: E. Jan Vardaman, TechSearch Int'l
Co-Chair: Mona Chopra, Motorola
Ball Grid Array packaging is an emerging technology. These papers address the
issues associated with bringing a new package technology to
production. Several authors examine the manufacturing challenges of
solder array connections and new concepts.
The Resin Molded Chip Size Package
Satoshi Tanigawa, Kazumasa Igarashi, Megumu Nagasawa, Nobuhiko Yoshio
Nitto Denko
Electrical Performance Trade-offs in BGA Package Designs
Kathy Wang
Digital Equipment Corp.
Mounting Technology of BGA-P & BGA-T
Dave Hattas, Art Wakigawa
Kyushu Matsushita
Low Cost Pad Array Chip Carriers Made With 3-Dimension-Conductivity Epoxy
Adhesives
Justin Bolger
Merix Corp.
Advanced Interconnect and Low Cost uStud BGA
Mamoru Mita, Geim Murakami, Toyohiko Kumakura, Norie Okabe,
Syouji Sinzawa
Hitachi Cable
An Overview of BGA Manufacturing
William Goers, Joel Mearig
EMPF
************************
Design for Manufacturing
Session W1B (8:30 - 11:15)
************************
Chair: CP Wong, AT&T Bell Labs
Co-Chair: Kam Yeung, AT&T Bell Labs
Design for Manufacture is a challenging area. While the need is recognized,
the applications have been lacking. This session looks at methods for
applying DFM in the electronics industry.
Applying DMF in the Semiconductor Industry
K. Preston White
U of Virginia
Development of DFM
Walt Trybula
SEMATECH
Design for Manufacturability and DFX Concepts, Applications and Perspectives
Hong-Chao Zhang
Texas Tech Univ.
Issues In Low-Cost Manufacture of Reliable Optoelectronic Switches
Scott Leclerc, Ganesh Subbarayan
University of Colorado at Boulder
Process Integration and Optimization of GaAs MESFET Integrated Circuit
Using Statistical Experimental Design Techniques
Jian Wang, C.C. Teng, J.R. Middleton, M. Feng
Univ. of Illinois at Urbana-Champaign
************************
Semiconductor Minifabs, Concepts and Implementation Issues II
Session W1C (8:30 - 11:15)
************************
Chair: L. Ken Keys, Louisiana State U.
Co-Chair: Robert Doering, Texas Instruments
This is Part 2 of a session that looks at manufacturing issues in the
semiconductor industry. The presentations range from management of
manufacturing flow to analysis of bottleneck equipment to select areas
for improvement.
Single-Wafer Processing: Opportunities & Challenges
Robert R. Doering
Texas Instruments
Low Volume VLSI Fab to Ensure Short Time to Market for Ericsson Telecom
Products
Kurt-Ingvar Engde
Ericsson
Batchless Factor Concept for Very Short Cycle Time Semiconductor
Manufacturing
Timothy D. Stanley
SEMATECH
The Impact of Single-Wafer Processing on Fab Cycle Time
Samuel C. Wood
Stanford University
Trends, Options, Challenges, Needs of Future Semiconductor Technologies,
and Products: A Summary View
L. Ken Keys
Louisiana State University
************************
Optional Tour
Wednesday 1:30 - 4:30 PM
Xetel
************************
You and your guests may register for the tour in advance on the registration
form or at the IEMT registration table. Cost is $25 each. Tour departs from
and returns to the hotel.
* * * * * Exhibits * * * * *
open all day Tuesday
If your company wishes to participate, contact:
TechSearch Int'l
IEMT Product Demonstrations
(see registration form for details)
A limited number of spaces is available
on a first come, first served basis
* * * * *
IEMT'95 Web Home Page.
The URL is: "http://naftalab.bus.utexas.edu/iemt95".
There are pointers to things to do and places to see in the Austin area.
The Hyatt Regency Austin
In the open atrium lobby, a free-flowing stream is surrounded by rock
waterfalls, and a wall of glass provides an uninterrupted vista of Town Lake
and the Austin skyline.
Preview the Proceedings
You can look over the Proceedings the week before the conference begins.
This way you can browse through it on the plane and show it to colleagues
for suggesting discussion questions at the conference. See registration form
for details.
Save $50
Join the IEEE before you register and use the member rates. You also
gain the benefits of membership including discounts on other conferences and
publications, portable insurance plans, and an opportunity to participate in
the world's largest professional society. Contact 800-678-IEEE or
member.services@ieee.org
Members of other professional societies may join the CPMT Society of the IEEE
and still receive member discounts and CPMT publications.
Coffee Break Sponsors
Your company name will be recognized in the final program and will be
displayed on a sign in the refreshment area. A table will be provided
near the sign to display informational and promotional literature about your
company.
To sponsor, call Pete Walsh at 703-907-7547. The fee is $150. Please
note that sponsorships must be prepaid, and must be received by
September 8 in order to be acknowledged in the final program.
* * * * * * * * * * * * * * *
Open the file "IEMT Reg Info" for complete registration information.
Return to Index
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CALL FOR PAPERS
46th Electronic Components and Technology Conference
Orlando, Florida
May 28-31, 1996
The ECTC offers papers covering a wide spectrum of topics, including
not only electronic components but also exciting new developments in
all areas of electronics technology (e.g., electronics assembly,
packaging, reliability, and materials). In 1995, over 200 presentations
(papers, posters, and short courses) from companies, universities, and
research institutes from around the world.
The aim of the conference is to continue to offer quality coverage of
technological innovations in the areas of design, materials, processes,
quality, and manufacturing for devices, components, and systems. This
we are particularly interested in the emerging areas of portable electronics,
flat panel displays, and wireless technologies.
Major topics include:
* Components * Connectors
* Interconnections * Manufacturing technology
* Materials and processing * Modeling and simulation
* Multichip packaging * Opto-electronics
* Quality and reliability * Single chip packaging
PAPER SUBMISSION
You are invited to submit ten (10) copies of a 500-word abstract
describing the scope, content, uniqueness, and key points of your
proposed paper to
Jim Billigmeier
3M Company
1 & C Sector Research Lab
3M Center
Bldg 201-1W-28
St. Paul, MN 55144-1000
Tel: (612)733-3090
Fax: (612) 737-5335
The abstracts must be received by October 16, 1995. You must enclose
your mailing address, business telephone number, facsimile number, and
email number with yor submission. Foreign authors should also include
a telex number
To expedite the review, please specify no more than two of the above
major topic areas that should consider your paper for presentation and
publication in the proceedings.
Authors will be notified of paper acceptance with instructions for
final paper presentation by November 16, 1995. Manuscripts are due
in final form for publication in the Conference Proceedings by
February 5, 1996.
FURTHER INFORMATION
Contact Bill Moody
Tel: (302) 478-4143
Fax: (302) 478-7057
Return to Index
Return to Conference Listing
SMTA 2nd Annual National Symposium
New and Critical Technologies for SMT
Research Triangle Park, North Carolina
October 23-26, 1995
Sponsored by SMTA (Surface Mount Technology Association)
Monday, October 23, 1995
Tutorial: Ball Grid Array Technology
Tutorial: SMT Compatible Chip on Board for MCM-L Applications
Tuesday, October 24, 1995
Session 1: Flip chip technology
Session 2: COB technology
Session 3: Reliability
Session 4: Conductive Adhesives
Wednesday, October 25, 1995
Session 5: Advanced packaging technology
Session 6: Chip scale packaging
Session 7: Solder technology
Session 8: PCB technology
INFORMATION
SMTA
5200 Willson Road, Suite 215
Edina, MN 55424-1343
Tel: (612) 920-7682
Fax: (612) 926-1819
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SPIE Microelectronic Manufacturing '95
Austin Marriott at the Capital
October 25-26, 1995
Austin, Texas, USA
CONFERENCE 2635: Microelectronic Manufacturing Yield, Reliability, and
Failure Analysis
Wednesday, October 25, 1995
Session 1: Yield Improvement
Session 2: Reliability (failure modes)
Thursday, October 26, 1995
Session 3: Reliability (manufacturing)
Session 4: Failure analysis
Session 5: Process enhancement
CONFERENCE 2636A: Microelectronic Device and Multilevel Interconnection
Technology
Wednesday, October 25, 1995
Session 1: Advanced device technologies
Session 2: Deep submicron devices I
Session 3: Deep submicron devices II
Session 4: Memory and silicide technology
Session 5: Advanced thin film dielectrics
CONFERENCE 2636B Multilevel Interconnection Technology
Thursday, October 26, 1995: Two sessions
CONFERENCE 2637: Process, Equipment, and Materials Control in
Integrated Circuit Manufacturing
Wednesday, October 25, 1995
Session 1: Control through equipment design, sensors, and monitors
Thursday, October 26, 1995
Session 2: In situ process monitoring and control
Session 3: Automation, environment control, and models
CONFERENCE 2638: Optical Characterization Techniques for High-Performance
Microelectronic Device Manufacturing
Wednesday, October 25, 1995
Session 1: Process diagnosis
Session 2: Advanced techniques
Session 3: Bulk and surface analysis
Thursday, October 26, 1995
Session 4: Advanced ellipsometry and reflectometry
Session 5: Process diagnosis
Session 6: Interconnects and imaging
Session 7: Bulk and surface analysis
Session 8: Laser scanning
INFORMATION
SPIE
P.O. Box 10
Bellingham, WA 98227-0010
Tel: (360) 676-3290
Fax: (360) 647-1445
SPIE On-line services: FTP and Telnet: spie.org
WWW: http://www.vestnet.no/org/spie.html/
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ISHM Advanced Technology Workshop on Flat Panel Display Packaging
San Antonio, Texas
November 15-17, 1995
Submitted by: Ron Pacheco
General Chair: Jack Balde, IDC (908) 788-5190
Program Cochairs: Ron Pacheco, Digital Equipment Corporation, (508) 493-0651;
and Jim Jorensen, Sandia National Laboratories, (505) 844-1023
WednesdayNovember 15
Registration: 10 am - 5 pm
Lunch: Noon - 1 pm
Keynote Addresses: 1 pm - 2 pm
Design and Manufacturing of Lightweight Portable Computers
Mark Foster, Engineering Director, Mobile Computing, Digital Equipment
Corporation, Personal Computer Business Unit
The Impact of Packaging Limitations in Head Mounted Displays
Scott Nelson, Honeywell
Break
Session 1: Lightweight Packaging
2:15 pm - 4:45 pm
Chairs:
Doug Baker, Compaq Computer Corporation
Stefan Peana, Motorola
Mechanical Engineering to Reduce Size and Weight of Portable Computers
Dan Bruner, Compaq Computer Corporation
Glass for ALMCD: Substrate Issues with Lower Weight Panels and Other
Technology Trends
Peter Bocko, Corning, Inc.
Weight Analysis of LCD Displays
Brandt Engstrom, Hitachi America
Reception: 5:30 pm - 6:30 pm
Dinner: 6:30 pm - 7:30 pm
Session 2: Interconnect Reliability
7:30 pm - 10 pm
Chair:
Ranjan Dutta, AT&T
Increasing Impact Reliabilty of LCD Based Products
Ron Larson and Suresh Goyal, AT&T Bell Labs
Assessing Reliability of LCD Displays during Manufacturing
Frank Libsch, IBM
Reliability of Thin Film Metallization in Displays
Ron Nowicki, Coloray
Stress Testing of Hand Held Display Products
Randy Burke, AT&T Network System
Thursday, November 16
Breakfast: 7 am - 8 am
Session 3: Display Technology Needs
8 am - 11 am
Chairs:
Hugo Steemers, Xerox PARC
Jim Jorgensen, Sandia National Labs
Packaging and Interconnect Concerns for Thin Film Electroluminescent
Displays
Frank Cupero, Westinghouse Norden Systems
Packaging and Interconnect Concerns for Plasma Display Panels
Doug Mansor, Photonics
Packaging and Interconnect Concerns for Field Emission Displays
Ron Hansen, Silicon Video Corporation
Packaging and Interconnect Concerns for Liquid Crystal Displays
Hugo Steemers, Xerox PARC
Reception: 5:30 pm - 6:30 pm
Dinner: 6:30 pm - 7:30 pm
Session 4: Device to Glass Interconnect
7:30 pm - 10 pm
Chair: Eric Bogatin, Echelle, Inc.
Optimization of Adhesive Characteristics for Chip on Glass Bonding
Karl Loh, Zymet, Inc.
Chip on Glass Interconnections using Anisotropically Conductive
Adhesives
Peter Hogerton, 3M Company
Optimization and Evaluation of Fine Pitch ACF Bonds to Glass
Thomas Todd, Toddco General, Inc.
Friday, November 17
Breakfast: 7 am - 8 am
Session 5: EMI/RFI Design Considerations
8 am - 11 am
Chairs:
Charles Guthrie, Dell Corporation
Brian Graham, Sharp Corporation
Design Flaws in Multilayer Display Interfaces Involving High Speed
Clocks:
A Case History
Todd Steigerwald, Dell Computer Corp.
High Speed Interconnect: A Cost Effective process for Flexible
Interconnects Requiring EMI Shielding and Controlled Impedance
Steve Dean, Parlex Corp.
Improving EMI Characteristics in Flat Panel Displays
Brian Graham, Sharp Electronics
EMI Issues for Flat panel Displays
Joe Miseli, Sun Microsystems
The Role of FPD Connectors in EMI Control
Larry Kopp, AMP, Inc.
Controlling EMI in Portable Computers
Low Voltage Differential Signal Interface for EMI Control
Jim Schuessler, National Semiconductor
While workshops generally invite papers and speakers, if there is interest in
participating in this workshop as a speaker, call the appropriate member of
the Program Committee for consideration.
Return to Index
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SHORT COURSES
ELECTRICAL DESIGN OF MULTI-CHIP MULTI-LAYER PACKAGING
Sunday, Oct. 1, 1995
8:30 am - 12:30 pm
Portland, Oregon
Submitted by: Alina Deutsch , EPEP Conf. Cochair.
A short course offered Sunday, October 1, 1995, Portland, Oregon,
the day before the 4th Topical Meeting on Electrical Performance
of Electronic Packaging EPEP'95, October 2-4, Portland, Oregon
Sponsored by IEEE, MTT, CPMT
Evan Davidson
George Katopis
IBM Corporation
Poughkeepsie, New York
OBJECTIVE
The intent of this short course is to introduce the attendees to an approach
that is useful for designing high performance MCMs. At the course's
conclusion, the student should understand the important technical issues and
have the knowledge to conduct MCM analysis and design. The course is
designed for an engineer who wants to understand more about MCMs and the
unique requirements for assuring that packages will be operational in the
above 100MHz. region of operation.
COURSE CONTENT
This course is based upon the practical experiences of the instructors who
have worked on many products using MCMs and it will stress the high frequency
design requirements for modern packages. The following topics will be covered:
* The "need" for MCMs
* An electrical design approach
* Power distribution design
* Circuit noise tolerance
* Signal distribution design
* Switching noise
* Crosstalk
* Design aid tools
* Acceptable ranges for key design parameters
The information presented will include the theoretical background with
practical methods for implementing a design for MCMs. These same techniques
can be applied to high frequency SCM-card designs. The class will be run
informally and interaction with the attendees is encouraged. Questions and
tangential discussions will be invited.
INSTRUCTOR BIOGRAPHIES
EVAN DAVIDSON
Evan Davidson is a Senior Technical Staff Member at IBM, Poughkeepsie. He
has been involved with package design for bipolar and CMOS mainframes for
the last 20 years. Mr. Davidson has actively participated in professional
societies throughout this period and he has given numerous presentations
and written several papers and articles on the subject of packaged
electronics. He also coauthored the electrical design chapter in the
"Microelectronics Handbook." He holds a BEE from Rensselaer Polytechnic
Institute, Troy, NY and an MSEE from New York University, NY, NY.
GEORGE KATOPIS
George Katopis is a Senior Engineer at IBM in Poughkeepsie, NY. For 15
years, he managed the group that implemented the design of MCMs in IBM's
mainframe computers. Previous to this assignment he pioneered in the area
of noise analysis and noise control in electronic packages. Mr. Katopis
has been an active participant in the IEEE with many talks and journal
articles in the area of digital noise. He is a coauthor of the electrical
chapter in the "Microelectronics Handbook." He received his BS in
electrical and mechanical engineering from the Technical University of
Athens, Greece in 1967. He has a MS and MPh from Columbia University, NY,
NY.
REGISTRATION
Participants interested in attending the short courses need to
register by AUGUST 14, 1995. Tutorials will be held only if enough
students register.
Please send
Name
Company/Affiliation
Address
City
State
ZIP
Phone
FAX
e-mail
REGISTRATION FEE (per person)
(includes course material and refreshments)
Half-day Course -name
---------------------------------------------------------$200.0
Full-Day Course -name
---------------------------------------------------------$375.0
Please make checks payable to:
University of Arizona
If you wish to use your VISA, MASTERCARD or DISCOVER
cards for registration:
Card no.
Exp. Date
Send information to the following address:
EPEP'95
Engineering Professional Development
University of Arizona
Box 9 Harvill Building, Room 235
Second and Olive Streets
Tucson, Arizona 85721
or e-mail:
baltes at bigdog.engr.arizona.edu
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UNDERSTANDING, PERFORMING, AND APPLYING
HIGH-FREQUENCY ELECTRICAL PACKAGE MEASUREMENTS
Sunday, Oct. 1, 1995
1:30 pm - 5:30 pm
Portland, Oregon
Submitted by: Alina Deutsch , EPEP Conf. Cochair.
A short course offered Sunday, October 1, 1995, Portland, Oregon,
the day before the 4th Topical Meeting on Electrical Performance
of Electronic Packaging EPEP'95, October 2-4, Portland, Oregon
Sponsored by IEEE, MTT, CPMT
Roger Marks, NIST, Organizer
John Pence, Cascade Microtech, Beaverton, OR
Dmitry Smolyansky, Intel Corp., Hillsboro, OR
Ed Godshalk, Tektronix, Inc., Beaverton, OR
OBJECTIVE
In this course, we survey the problems and solutions. We review the basic
parameters, including scattering parameters and impedances, and present a
form readily applicable to planar transmission lines. We review both
frequency-domain and time-domain network analyzers and calibration methods,
and we present an example of the application of accurate measurements to the
analysis of a multichip module.
COURSE CONTENT
For digital as well as RF or microwave packages, high-speed and microwave
electrical measurements provide a probe of electrical performance that can be
significantly more accurate than simulation results. However, without a good
understanding of the inherent errors and the calibration methods available to
compensate for them, even state-of-the-art instrumentation does not ensure
accurate measurement. The following topics will be covered:
* Network Analyzer Calibration and Measurement (Marks)
* Time Domain Network Analysis (Smolyansky)
* Package Probing Technology (Pence)
* Analysis of Multichip Modules by Accurate Measurement (Godshalk)
This course will be useful to engineers involved in design, processing, or
product specification who need to understand the opportunities and limitations
of accurate electrical measurements.
INSTRUCTOR BIOGRAPHY
ROGER MARKS
Roger Marks graduated in Physics from Princeton University and received
his Ph.D. in Applied Physics from Yale University. Since 1988, he has
been with the Electromagnetic Fields Division of the National Institute of
Standards and Technology in Boulder, CO, where he has investigated
electromagnetic and instrumentation problems related to the microwave
characterization of high speed microelectronic circuits. He has developed
fundamental theory as well as numerous calibration and measurement
methods, including the multiline TRL method, and has been involved in many
cooperative projects with industry. In recognition of this work, he has
received several awards, including the 1995 IEEE Morris E. Leeds award
"for the development of measurement methods for accurate on-wafer
characterization of monolithic microwave integrated circuits." Dr. Marks
is the author or coauthor of over 60 technical publications.
REGISTRATION
Participants interested in attending the short courses need to
register by AUGUST 14, 1995. Tutorials will be held only if enough
students register.
FOR REGISTRATION INFORMATION, SEE "Electrical Design of Multi-chip Multilayer
Packaging" above
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PRACTICAL EMC DESIGN AND MODELING
Sunday, Oct. 1, 1995
1:30 pm - 5:30 pm
Portland, Oregon
Submitted by: Alina Deutsch , EPEP Conf. Cochair.
A short course offered Sunday, October 1, 1995, Portland, Oregon,
the day before the 4th Topical Meeting on Electrical Performance
of Electronic Packaging EPEP'95, October 2-4, Portland, Oregon
Sponsored by IEEE, MTT, CPMT
Prof. Todd Hubing
University of Missouri-Rolla
Rolla, Missouri 65401-0249
Dr. Barry Rubin
IBM T.J. Watson Research Center
Yorktown Heights, N. Y. 10598
OBJECTIVE
The intent of this course is to give the student a basic understanding of the
issues in electromagnetic compatibility as it pertains to the design of
tabletop electronic systems. The student will learn about the sources of
radiation and how radiated emissions can cause problems with other systems and
with meeting established governmental regulations. The student will learn the
fundamentals of tools used to calculate radiated emissions and how to develop
simple models that represent the salient features of real products.
COURSE CONTENT
The course is based on the theoretical and practical knowledge of instructors
who have spent many years analyzing and gaining understanding in the area of
radiation from electronic products.
The course will cover the following topics:
* Overview of EMC
* History
* examples of common problems
* radiated and conducted EMI
* RF susceptibility
* ESD
* common EMC fixes
* EMC Design Strategies
* PCB design guidelines
* MCM design guidelines
* decoupling
* design trends (impact on EMC)
* Theoretical Issues
* Differential mode radiation
* Common mode radiation
* Sources
* Modeling structures as antennas
* Modeling Structures
* What structures can be modeled
* Theory behind MOM (Boundary Element) and Finite methods
* Limitations in rigorous tools
* Understanding limitations of "fast" tools
* How to set up card structures, cable structures, and box-aperture
problems
* How to simplify models
* Gridding issues for MOM solvers
* Interpreting results
* Common errors
* Questions & Discussion
INSTRUCTOR BIOGRAPHIES
TODD H. HUBING
Todd Hubing is an Associate Professor of Electrical Engineering at the
University of Missouri-Rolla. He teaches courses in electromagnetic
compatibility, antennas, and basic and advanced electromagnetic theory. As
one of the principal faculty members in the UMR Electromagnetic
Compatibility Laboratory, he directs research relating to electromagnetic
interference problems with high-speed electronic systems. Prior to joining
the University of Missouri-Rolla in 1989, Dr. Hubing was an EMC engineer in
the Radiation Engineering Department at IBM in Research Triangle Park, NC.
He holds a BSEE degree from the Massachusetts Institute of Technology, an
MSEE degree from Purdue University, and a Ph.D. from North Carolina State
University.
BARRY J. RUBIN
Barry Rubin is a Research Staff Member at IBM T. J. Watson Research Center.
Dr. Rubin has been involved, since 1976, on all aspects of electrical
package analysis. He has developed powerful techniques for the extraction of
package parameters and the calculation of radiated emissions from electronic
systems, and has published extensively in these areas. He received the BEEE
degree from the City College of NY, the MSEE degree from Syracuse
University, and holds a Ph.D from the Polytechnic Institute of NY.
REGISTRATION
Participants interested in attending the short courses need to
register by AUGUST 14, 1995. Tutorials will be held only if enough
students register.
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THE DESIGN AND PACKAGING OF RF WIRELESS SYSTEMS
Sunday, Oct. 1, 1995
8:30 am - 5:30 pm
Portland, Oregon
Submitted by: Alina Deutsch , EPEP Conf. Cochair.
A short course offered Sunday, October 1, 1995, Portland, Oregon,
the day before the 4th Topical Meeting on Electrical Performance
of Electronic Packaging EPEP'95, October 2-4, Portland, Oregon
Sponsored by IEEE, MTT, CPMT
Saila Ponnapalli
Brian Gaucher
IBM T.J. Watson Research Center
P.O. Box 218
Yorktown Heights, N. Y. 10598
OBJECTIVE
The intent of this course is to first provide a high level introduction to
communication systems and using this as a foundation, provide a more
detailed focus on RF systems and packaging considerations.
Packaging issues are reasonably well understood in digital applications. At RF
frequencies, however, packaging issues become more complicated and effects
which can be neglected in the digital domain become crucial performance
considerations. In this course, high level radio systems and fundamental
considerations in electrical analysis of packages are studied and the
relationships between radio subsystems and packaging considerations are
outlined. Theoretical analysis and simulations will be presented followed by
practical examples and problems. Attendees will leave the course with a strong
sense of how packaging and RF performance inter-relate, how problems can be
detected both on the bench and with prediction tools, and methods to
ameliorate them.
COURSE CONTENT
The following topics will be covered:
* Radio System Level Issues-
* Data Rate, Throughput, Modulation Schemes, Performance Metrics etc.
* Radio Component Block Definitions-
* Mixers, Modulators, Demodulators, LNAs, PAs, Filters, Synthesizers,
etc.
* Packaging Considerations-
* Electrical Analysis, EMI/EMC, Coupled Noise, Delta-I Noise, Modeling
and Software Tools, Package Performance Metrics etc.
* Impact of Packaging on Component and System Performance-
* FCC Considerations, Radio Component Packaging, Antennas and Package
Effects, Packaging Effects on Radio Performance Metrics-Receiver
Sensitivity, Throughput, Practical Problems, etc.
The class will encourage discussions and experimental techniques will be
explained.
INSTRUCTOR BIOGRAPHIES
SAILA PONNAPALLI
Saila Ponnapalli received her PhD in December 1990 from Syracuse
University specializing in numerical aspects of electromagnetics. She
worked at Lockheed's Palo Alto research lab during the summer of 1988
where she performed research in novel algorithms in electromagnetics. She
joined IBM T.J. Watson Research in May 1991 and is currently a Research
Staff Member. At IBM she has been involved in theoretical and applied
work in the electromagnetics, packaging and RF arenas. She developed two
tools for IBM, a method of moments based tool to analyze radiation from
antennas and EMI problems for packaging applications, and a tool to
compute package parasitics for package structures. She was involved with
analyzing timing and delay characteristics of MCM and card-on-board
packages for an IBM mainframe product. Over the past few years, she has
been in the RF wireless group, where she has designed and developed
several antennas for IBM products, and has been involved in analysis of
packaging issues related to RF wireless systems. She has written several
technical papers and chapters in books. She is an active member of Tau
Beta Pi, Sigma Xi and IEEE.
BRIAN GAUCHER
Brian Gaucher performed his undergraduate work at the University of
Massachusetts specializing in RF and Microwave design. He received his
graduate degree in Electrical Engineering from North Eastern University
specializing in Digital Communication systems. >From 1981-83 he worked at
Alpha Industries performing research and design of GaAs FET amplifiers
and super components. In 1983, Brian took a position at GTE in Needham,
MA where he worked on a variety of state of the art communication and
radar systems ranging from 1 to 60 GHz for the military. These included
Direct Sequence and Frequency Hopping systems as well as frequency
chirped radar applications. He was an active Principle Investigator
throughout his career at GTE working on projects from millimeter wave
components to hand held spread spectrum transceivers. In 1993, he took a
position at IBM's T. J. Watson Lab where he has been working on novel
wireless computing methods and products. Since joining IBM's
Communications Technology department, he has helped three products to the
market place. Brian has authored numerous internal and classified papers,
he is an active member of the IEEE and listed in the Who's Who Among
American Engineers.
REGISTRATION
Participants interested in attending the short courses need to
register by AUGUST 14, 1995. Tutorials will be held only if enough
students register.
FOR REGISTRATION INFORMATION, SEE "Electrical Design of Multi-chip Multilayer
Packaging" above
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SPICE: Application to Signal Integrity Analysis
Sunday, Oct. 1, 1995
8:30 am - 12:30 pm
Portland, Oregon
Submitted by: Alina Deutsch , EPEP Conf. Cochair.
A short course offered Sunday, October 1, 1995, Portland, Oregon,
the day before the 4th Topical Meeting on Electrical Performance
of Electronic Packaging EPEP'95, October 2-4, Portland, Oregon
Prof. Olgierd A. Palusinski
Dept. of ECE Univ. of Arizona
Tucson, AZ 85721
OBJECTIVE
This 4 hour course will povide basics in design of electronic circuits and
systems for signal integrity, describe tools derived from the Simulation
Program with Integrated Circuit Emphasis (SPICE), and demonstrate their use.
Important features of SPICE will be described, limitations of the program will
also be discussed, and recommendations for efficient use of SPICE control
parameters will be given. The course is recommended for engineers dealing with
circuit and package electrical problems.
COURSE CONTENT
The following topics will be covered:
* Signal transmission in circuits and packages, basic issues.
* SPICE numerical methods, control parameters (options), device models.
* SPICE modifications for simulation of coupled transmission lines,
LSPICE program for systems with lossless lines, LSPICE3 for systems
with lossy lines (DC losses).
* Beyond SPICE: SPEC spectral simulator, basic features, applications
to RF circuits.
* SPEC Power Tools: programs for automation of multiple analysis runs,
optimization, sensitivity studies, parameter sweeps, processing of
output data.
Demonstration of SPICE modifications, and other related software developed at
the University of Arizona for public domain is planned.
INSTRUCTOR BIOGRAPHY
OLGIERD A. PALUSINSKI
Olgierd A. Palusinski is a Professor in the Department of Electrical and
Computer Engineeering at the University of Arizona, where he teaches and
conducts research in simulation of integrated circuits and electronic
packaging. He spent his recent sabbaticals and the last three summers at
Motorola's Advanced Packaging Development Center carrying on research on
electrical design of RF packages. Dr Palusinski received his M.S. and
Ph.D. degrees in Electrical Engineering from the Technical University of
Silesia,Poland. He also studied n France, where he received the Degree
"Docteur de l'Universite de Lille" from the University of Lille.
REGISTRATION
Participants interested in attending the short courses need to
register by AUGUST 14, 1995. Tutorials will be held only if enough
students register.
FOR REGISTRATION INFORMATION, SEE "Electrical Design of Multi-chip Multilayer
Packaging" above
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EXPERIMENTAL CHARACTERIZATION OF ELECTRONIC PACKAGING
Sunday, Oct. 1, 1995
8:30 am - 12:30 pm
Portland, Oregon
Submitted by: Alina Deutsch , EPEP Conf. Cochair.
A short course offered Sunday, October 1, 1995, Portland, Oregon,
the day before the 4th Topical Meeting on Electrical Performance
of Electronic Packaging EPEP'95, October 2-4, Portland, Oregon
Dr. Michael Steer, Associate Professor
Electrical and Computer Engineering Dept.
North Carolina State University,
Raleigh,NC 27695-7911
OBJECTIVE
The intent of this half-day course is to introduce the attendees to the most
common type of measurement techniques used in characterizing signal integrity
and noise signals on packaging interconnections ranging from multi-chip
modules to printed-circuit boards to on-chip wiring.
COURSE CONTENT
The following topics will be covered:
* Modeling for Signal Integrity
* Requirements
* Measurement Tools
* Time domain reflectometer, network analyzer, LCR meter.
* Electrical Characterization of Interconnects
* Developing a Package Model
* IBIS Signal Integrity Models of Off-Chip Drivers and Receivers
* Signal Integrity CAE Solutions
* Questions & Discussion
INSTRUCTOR BIOGRAPHY
MICHAEL STEER
Michael Steer is director of the Electronics Research Laboratory and is an
Associate Professor of Electrical and Computer Engineering at North Carolina
State University. He received his Ph.D. in Electrical Engineering from the
University of Queensland, Brisbane, Australia, in 1983 and has been at North
Carolina State University since then. His expertise is in the areas of
computer aided engineering of microwave circuits and of the packaging of
high speed digital systems. He specializes in the measurement technology
required for the electrical characterization for signal integrity purposes.
He has undertaken the electrical characterization of interconnects at the
printed circuit board, multi-chip module, and chip level. He is the model
librarian of the IBIS consortium which is developing signal integrity
models of off-chip drivers and receivers for the purposes of signal
integrity simulation.
REGISTRATION
Participants interested in attending the short courses need to
register by AUGUST 14, 1995. Tutorials will be held only if enough
students register.
FOR REGISTRATION INFORMATION, SEE "Electrical Design of Multi-chip Multilayer
Packaging" above
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ELECTRICAL DESIGN AND CHARACTERIZATION OF PACKAGES
Sunday, Oct. 1, 1995
8:30 am - 12:30 pm
Portland, Oregon
Submitted by: Alina Deutsch , EPEP Conf. Cochair.
A short course offered Sunday, October 1, 1995, Portland, Oregon,
the day before the 4th Topical Meeting on Electrical Performance
of Electronic Packaging EPEP'95, October 2-4, Portland, Oregon
Prof. Madhavan Swaminathan
Packaging Research Center
Prof. Joy Laskar
School of Electrical and Computer Engg.
Georgia Institute of Technology Atlanta, Georgia 30332
OBJECTIVE
Low-cost packaging of electronics will be one of the fastest-growing and
fundamental staple technologies as we enter the 21st century - a century which
will be characterized by the ever-increasing application of microelectronics
to both consumer and industrial electronics. Along with the thrust on
low-cost, industries are aiming towards high-performance, multifunctional and
portable units. This would not be possible without considerable emphasis on
design and characterization techniques for packages. This course will
highlight the packaging trends and review design and characterization methods
for packages operating over a wide bandwidth, with emphasis on application.
COURSE CONTENT
The following topics will be covered:
* Packaging Trends and Technology Overview
* SCM, MCM and PCB design issues
* Frequency and Time domain calibration techniques
* Electrical Design Issues such as interconnection cross-section,
signal integrity, skew, cross-talk, reflected noise and switching
noise
* Broadband Characterization Techniques
* Interconnect Characterization and Design
* Application specific design issues with emphasis on digital and
mixed-signal circuits.
The course is intended to be a practical course and is intended for industry
engineers working in the design, signal integrity, characterization and
application areas.
INSTRUCTOR BIOGRAPHIES
MADHAVAN SWAMINATHAN
Madhavan Swaminathan received the B.E. degree in electronics and
communication from Regional Engineering College, Tiruchi, India in 1985 and
the M.S. and Ph.D. degrees in electrical engineering from Syracuse
University in 1989 and 1991, respectively. He is currently an Adjunct
Professor in the School of Electrical and Computer Engineering and member
of the Research Staff at the Packaging Research Center, Georgia Institute of
Technology, Atlanta, Georgia. During his graduate study, he was involved in
the numerical modeling of waveguides, antennas and transmission lines for
microwave applications and their implementation on parallel computers. In
1990, he joined the Advanced Technology Division of the Packaging
Laboratory at IBM, E.Fishkill, New York where he was involved with the
design, analysis, measurement and characterization of packages for high
performance systems, and low-cost multilayer thin-film technology. He was
involved in the design and characterization of packages for the OEM market
such as in wireless, automotive and consumer applications. He joined the
Packaging Research Center at Georgia Tech in October 1994. Dr. Swaminathan
has over 35 publications in refereed journals and conferences and has four
inventions in the area of packaging.
JOY LASKER
Joy Laskar received the B.S. degree (Computer Engr., highest honors) from
Clemson University in 1985. He received the M.S. and the Ph.D. degrees in
Electrical Engineering from the University of Illinois at Urbana-Champaign
in 1989 and 1991 respectively. His doctoral research was concerned with the
experimental study and optimization of the high frequency device
performance of compound semiconductor transistors. In 1985 he was employed
at IBM's Thomas J. Watson research center, where he studied hot-electron
effects in sub-micron CMOS technology. From 1991 to 1992 he served as
Visiting Assistant Professor at the University of Illinois. From 1992 to
1994 he served as Assistant Professor at the University of Hawaii at Manoa.
Since 1995 he has been an Assitant Professor in the School of Electrical and
Computer Engineering at Georgia Tech. Most recently, Dr. Laskar has been
primarily concerned with wide bandwidth on-wafer characterization
techniques up to 110 GHz with applications to monolithic microwave
integrated circuits (MMICs) and high speed packages. Dr. Laskar has
published over 30 peer revie wed articles in IEEE and APS journals.
REGISTRATION
Participants interested in attending the short courses need to
register by AUGUST 14, 1995. Tutorials will be held only if enough
students register.
FOR REGISTRATION INFORMATION, SEE "Electrical Design of Multi-chip Multilayer
Packaging" above
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IEEE CPMT INFORMATION
Submitted by Paul Wesling:
The Table of Contents for upcoming/current issues of the IEEE Trans.
on Advanced Packaging can be browsed, to see what topics and papers
are being included. For example, the May issue of this quarterly
journal has a special section of six papers on the topic of
optoelectronics packaging, edited by R. Boudreau, and a second section
of 6 papers on Adhesive Joining Technology in Electronics Manufacturing,
edited by J. Morris. There are other sections on flip-chip packaging,
multichip modules, electrical performance modeling, and other topics in
this issue.
To browse the Table of Contents, access the WEB server at
http://www.ieee.org/pub_preview/cpmtb_toc.html
Each quarter, this location will be updated with the next Table of Contents.
For information on subscribing to this quarterly journal (800 pages/year;
about 100 papers), call IEEE (in the USA tollfree at 1-800-678-IEEE) and
ask for publication 021-1651. Subscriptions are $250/year (non-IEEE
members). You may wish to join IEEE (members get substantial discounts);
if so, request information from IEEE or contact p.wesling@ieee.org for
information.
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