CPMT INFORMATION
CONFERENCES AND WORKSHOPS
ETIM'96
1996 International Workshop on Emergent Technologies
for Instrumentation and Measurements
Como, Italy - 10-11 June 1996
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Submitted by:
Vincenzo Piuri
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Organized by the IEEE Instrumentation and Measurement
Society (Technical Committee on Emergent Technologies)
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CALL FOR PAPERS
This workshop is directed to create a unique synergetic discussion forum on
the emergent technologies and a strong link between the
theoreticalresearchers and the practitioners in the application
fields related to instrumentation and measurements. The
two-days single-session schedule will provide the ideal environment
for in-depth analysis and discussions concerning the theoretical aspects of
the applications and the use of new technologies in the practice.
Researchers and practitioners are invited to submit papers concerning
theoretical foundations, experimental results, or practical applications
related to the use of advanced technologies for instrumentation and
measurements. Papers are sollicited on, but not limited to, the
following topics: neural networks, fuzzy logic, genetic algorithms, virtual
instruments, optical technologies, laser, advanced digital signal/image
processing, advanced analog signal processing, wavelets, sensor technologies,
remote sensing, distributed systems, fault tolerance, adaptive systems.
Interested authors should submit an extended summary or the full paper
(limited to 20 double-spaced pages including figures and tables) to the
program chair by January 15, 1996 (PostScript email or readable
fax submissions are strongly encouraged). Submissions should contain: the
corresponding author, affiliation, complete address, possible fax and email
addresses. Submission implies the willingness of at least one of the authors
to register and attend at the workshop and to
present the paper. The corresponding author will be notified by February 16,
1996. The camera- ready version is limited to 10 one-column
IEEE-book-standard pages and is due by May 1, 1996.
The workshop will be held at the "A. Volta" Research Center - Villa Olmo, in
Como, Italy. It is a two-hundred years-old villa in the pleasant scenario of
one of the most attractive lakes around the nothern Italy, near Milan. Easy
and frequent connections by train and airplane are available from Milan and
all the main cities in Europe; flights from US and Asia arrive to
the Malpensa international airport, connected by bus to Milan. The
registration fee will be 120 US$, including lunches, coffe breaks and one
copy of the proceedings. Hotel reservation will be managed directly by the
Research Center to provide highly discounted rates.
Program Chair
prof. Vincenzo Piuri
Dept of Electronics and Information
Politecnico di Milano
piazza L. da Vinci 32
I-20133 Milano, Italy
phone +39-2-2399-3606
fax +39-2-2399-3411
e-mail piuri@elet.polimi.it
American Co-Chair
prof. Emil Petriu
Dept. of Electrical Engineering
University of Ottawa
Ottawa, Ontario, Canada K1N 6N5
phone +1-613-564-2497
fax +1-613-564-6882
email petriu@trix.genie.uottawa.ca
Asian Co-Chair
prof. Kenzo Watanabe
Research Inst. of Electronics
Shizuoka University
3-5-1 Johoku, Hamamatsu 432, Japan
phone +81-534-71-1171-573
fax +81-534-74-0630
email watanabe-k@rie.shizuoka.ac.jp
Workshop Secretariat
Ms. Laura Caldirola
Politecnico di Milano
phone +39-2-2399-3623
fax +39-2-2399-3411
caldirol@elet.polimi.it
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CALL FOR PAPERS
IEEE 1996 INVMTC
Int'l Non-Volatile Memory Technology Conference
June 24-26, 1996
Holiday Inn-Pyramid, Albuquerque, New Mexico, USA
Submitted by:
W. D. Brown
Sponsored by:
IEEE Components, Packaging, and Manufacturing Technology Society
and
the IEEE Computer Society
in cooperation with the
Solid-State Circuits Council and the IEEE Magnetics Society
The IEEE 1996 INVMTC is the premier international forum for the
presentation of NVM technology options. The conference's mission is to
promote communication between NVM technologists and users. Its scope
includes all classes of implementation technologies, and applications from
very small to very large storage systems. The technical program embraces
current and emerging approaches, and present and future system
requirements. Technologies include, but are not limited to, semiconductor,
magnetic, and optical NVM. Technology and applications are emphasized, and
overview analyses and comparison studies are of interest.
Topics of Interest:
Emerging Storage Requirements, Current NVM Research Topics, New Memory
Media, Mass Storage Systems, Space Storage Systems, Avionics and Missile
Storage, Crash Recorder Technology, Mainframe Storage Systems, PC Storage
Systems, Packaging Technology, Memory Card Technology, Memory Power
Management, Error Control Approaches, Magnetic and Optical Disks, Magnetic
and Optical Tapes, Miniature Recording Technology, Magnetoresistive Memory,
Bloch Line Technology, Ferroelectric Memory, Flash Memory, EEPROM Devices,
SONOS Devices, CMOS/Battery Devices, and Analog Storage Devices
Abstract Submission Information:
Abstracts are due January 16, 1996.
Authors will be notified of accepted abstracts by March 4, 1996.
Abstracts of proposed papers should range from 300-500 words.
Abstracts, written in English, can be submitted by email (ASCII
text), FAX, or mail, to: Gail Wesling, Chappell Enterprises, 12250
Saraglen Dr., Saratoga, CA 95070, USA. Phone: (408)257-5702, FAX:
(408)285-9670, Email: g.wesling@ieee.org
Please include the following with each abstract: Paper title,
author list, company/institution, and contact author, address,
phone, FAX, and e-mail address. Note: Correspondence will be
conducted electronically, so please provide accurate FAX/e-mail
information.
The abstract must clearly describe the nature, scope, content,
key points, and significance of the proposed paper, and must
consist of work and results not published previously. Student
participation is encouraged.
Submitting an abstract represents a commitment to submit a
cleared manuscript by April 15, 1996; and either to attend the
conference or to send a knowledgeable substitute who can answer
questions regarding the reported work. Authors are responsible for
obtaining internal approvals consistent with these deadlines.
Copies of papers may be shown to members of the technical press for
pre-conference publicity, who may choose to quote up to 50 words
from a paper and publish selected figures and diagrams. If this
would create a problem, please specify this when submitting the
abstract.
While the IEEE 1996 INVMTC is sponsored by the IEEE, IEEE
membership is not required to submit an abstract and to present a
paper, nor to attend the conference.
Publication Information:
Camera-ready papers for publication in the conference
proceedings are expected to be four pages in length, including
diagrams, figures, and photographs. The due date for accepted
papers is April 15, 1996.
Full instructions for publications will be provided. Selected
authors will be invited to submit a full paper for inclusion in a
special issue of the "IEEE Transactions on CPMT." Papers published
in the proceedings are eligible for publication in the "IEEE
Transactions on CPMT" after normal review procedures.
As a service to busy authors and to authors for whom English
is a second language, Chappell Enterprises will format and edit
papers from text files supplied on diskette or by email, for an
additional fee.
Copies of past INVMTC proceedings are also available for
purchase.
Exhibitors' Information:
Exhibit space will be available to exhibitors at the IEEE 1996
INVMTC. The cost to exhibitors will be the nominal conference
registration fee. For information, please contact Gail Wesling,
Chappell Enterprises, 12250 Saraglen Dr., Saratoga, CA 95070, USA,
Phone: (408)257-5702, FAX: (408)285-9670, Email: g.wesling@ieee.org
Conference Steering Committee:
General Chair: W. D. Brown, University of Arkansas, 3217 BELL,
Fayetteville, AR 72701, USA; Phone: (501)575-6045, FAX:
(501)575-7967, Email: wdb@engr.uark.edu
Committee Chair: J. Brewer, Westinghouse, Inc., 351 White
Cedar Lane, Severna Park, MD 21146-3335, USA; Phone: (410)765-1247,
FAX: (410)765-1468, Email: j.brewer@ieee.org
Technical Program: R. L. Wiker, Honeywell, Inc., 13350 US Hwy
19 N, Clearwater, FL 34624-7290, USA; Phone: (813)539-2357, FAX:
(813)539-2558, Email: wiker_r_l@space.honeywell.com
Technical Program - Asia: E. Takeda, Hitachi, Ltd., CRL., P.O.
Box 2, Kokubunji, Tokyo 185, JAPAN; Phone: (81)423-23-1111, FAX:
(81)423-27-7699, Email: etakeda@crl.hitachi.co.jp
Technical Program - Europe: H. Maes, IMEC, Kapeldreef 75,
B-3001, Leuven, Belgium; Phone: (32)16-281-283, FAX:
(32)16-281-501, Email: maesh@imec.be
Local Chair: M. G. Knoll, Sandia National Lab, Dept.
1341/MS1074, Albuquerque, NM 87185, USA; Phone: (505)845-8525, FAX:
(505)844-8480, Email: knollmg@smtplink.mdl.sandia.gov
Finance: D. W. Williams, Westinghouse, Inc., Box 1521/MS 3D12,
Baltimore, MD 21203, USA; Phone: (410)765-9748, FAX: (410)765-7652,
Email: williams.d.w@nort.bwi.wec.com
Exhibits: R. Fedorak, Naval Air Warfare Center, Code 5053,
Warminster, PA 18974, USA; Phone: (215)441-1278, FAX: (215)441-7271
Publicity: R. Katti, CSMT, Jet Propulsion Lab, Caltech, MS
300-329, 4800 Oak Grove Dr., Pasadena, CA 91109, USA; Phone:
(818)354-3054, FAX: (818)393-4820, Email: katti@vlsi.jpl.nasa.gov
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CALL FOR PAPERS
IEEE CICC
IEEE Custom Integrated Circuits Conference
.... the leading edge of ICs
May 5 - 8 ,1996
San Diego, CA
Submitted by:
Brian Antao
Sponsored by:
IEEE Electron Devices Society
in cooperation with the
IEEE Solid State Circuits Council.
web site for CICC for more info is:
http://uivlsi.csl.uiuc.edu/~brian/cicc.html
CICC is the premier conference devoted to IC development. It provides a
forum for circuit designers, CAD developers, manufacturers and ASIC users
to present and discuss exciting new developments, future trends and innovative
ideas. It provides an unique platform and an opportunity for the CAD
developers and the designers to interact and exchange ideas for developing
leading edge CAD solutions to the many design problems.
CONFERENCE HIGHLIGHTS
Technical Papers: The focal point of CICC: approximately 140 papers
addressing a broad range of leading-edge circuits, applications, design
techniques and tools will be presented. Instructions for potential
contributors are given below.
Panels: Discussions and debates by industry leaders on key issues, problems,
solutions and potentials of the IC industry.
Educational Sessions: A full day of extended tutorials offer a unique and
valuable opportunity for practicing professionals to get acquainted with
aspects of ASIC development outside of their specialties.
Exhibits/Exhibit or Sessions: CICC includes extensive exhibits by ASIC,
EDA and test/measurement vendors. Exhibitors are also invited to give
presentations on new products and capabilities in special exhibitor
sessions. Contact the Exhibits Chairman for details.
SUBMISSION OF PAPERS
Deadline December 6, 1995 Prospective authors must submit CAMERA-READY
papers, up to four pages in length inclusive of all illustrations, charts
and tables. Those interested in submitting papers should contact the
Conference Manager as early as possible to obtain an author's kit and
detailed instructions.
The address is:
Melissa Widerkehr,
CICC, 101 Lakeforest Boulevard,
Suite 270, Gaithersburg,
MD, 20877,
Telephone: (301)-527-0902,
Fax: (301)-527-0994.
Email: Widerkehr@aol.com
ACCEPTED PAPERS WILL BE PRINTED IN THE PROCEEDINGS WITHOUT OPPORTUNITY FOR
FURTHER CHANGE.
The paper should report original and previously unpublished work,
including specific results. Circuit oriented work must include measured
experimental results.
Deadline for RECEIPT of technical papers is December 6, 1995.
Appropriate company and government clearances MUST be obtained prior to
submission. After receipt of the author kit, the completed original and
25 copies should be sent to the Conference Manager at the address above.
Authors of accepted papers will be notified by mail by January 31, 1996.
PAPERS IN THE FOLLOWING AREAS ARE REQUESTED:
Analog and Mixed-Signal Circuits and Systems:
Data convertors, modulators, filters, high speed analog, low voltage
techniques. Mixed analog-digital IC applications, disk read/write
channels, RAMDACS.
Digital Signal Processing: Image compression, recognition, and enhancement
particularly for digital video. Voice coding and recognition.
Specialized processing function architectures. Digital filtering,
encryption, HDTV, video conferencing, multimedia, graphics controllers,
video drivers.
Communications: Data, voice and image transmission. Digital, analog
modulation, equalization, error correction, coding, switching.
SONET/SDH, ISDN, LAN/WAN/ATM and broadband applications. Wireless and
RF submissions are encouraged.
Custom Application Specific Circuits: Innovative designs for cell-based
circuits, full custom ICs and ASIC memories. Novel design concepts, low
power low voltage circuits, high-performance circuits, architectures or
system applications (automotive, bio-medical, etc.) are of particular
interest.
Gate Arrays and Programmable Devices: GA, EPLD, FPGA, PAL, PLA devices,
circuits and architectures,
as well as the CAD tools targeting these devices. Device applications
are encouraged.
Design Automation - Design Capture:Logic and high-level synthesis and
optimization, innovative design capture techniques, frameworks, user
interfaces.
Design Automation - Physical Design: Silicon compilation, module
generation, symbolic layout, automatic place and routing techniques,
circuit parameter extraction and circuit verification.
Simulation and Modeling:Device or process modeling, circuit, functional,
timing or logic simulation with emphasis on analog modeling, multi-chip
modules and mixed-signal simulation. Submissions are encouraged in the
power estimation and analysis areas for low-power design, RF modeling
and simulation; and interconnect and packaging issues for simulationa
and modeling.
Fabrication and Assembly: Developments in process integration, quick-turn
manufacturing, MOS, bipolar, BiCMOS, smart power and GaAs, multichip
modules, package modeling, ESD protection, fiber optic tranceivers.
Testing and Reliability: Advances in design-for-testability (DFT), fault
modeling and grading, IDDQ measurements, parametric characterization,
high speed or high frequency measurement techniques and failure analysis.
Library Development and Design Methodology: Cell library generation and
characterization, reusable and customizable megacells, Algorithim to
Silicon design flows.
FURTHER INFORMATION
For complete author kit instructions, registration information and general
inquiries contact the Conference Manager:
Melissa Widerkehr,
Custom Integrated Circuits Conference,
101 Lakeforest Boulevard,
Suite 270, Gaithersburg,
MD, 20877,
Telephone: (301)-527-0902,
Fax: (301)-527-0994.
Email: Widerkehr@aol.com
Further information can also be obtained from:
Bob Cordell, Technical Program Chair,
Bellcore,
331 Newman Springs Road, Room 3Z-307,
Redbank, NJ 07701,
telephone: (908)-758-2963
email: rrc@nyquist.bellcore.com
OR
Jake Buurma, Conference Chair,
7115 Raich Drive,
San Jose, CA, 95120,
telephone: (408)-268-2576.
email: jake.buurma@taec.com
Potential Exhibitors should contact the Exhibits Chair:
Brian Fitzgerald,
IBM Corporation,
404 Wyman Street,
Waltham, MA, 02254,
telephone: (617)-895-1338.
email: fitzgerald@vnet.ibm.com
=======================================================================
See the CICC'96 WWW site for more information at :
http://uivlsi.csl.uiuc.edu/~brian/cicc.html
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Second Call For Papers
ADHESIVES IN ELECTRONICS '96
2nd International Conference on Adhesive Joining & Coating Technology
in Electronics Manufacturing
June 3-5, 1996
Stockholm, Sweden
Submitted by:
James Morris
In cooperation with:
IEEE CPMT Society
VDI/VDE-IT
IPC
ABSTRACT DUE DATE: 200-300 word abstract in English is due 23 DECEMBER, 1995
The abstract should clearly describe the nature, scope, key points and
significance of the paper. It should also present the experimental
methodology and significant results achieved. Paper selections will be made
by 29 February 1996 and final CAMERA-READY manuscripts of accepted papers
will be due 19 April 1996
Note: Selected papers may be requested for journal publication.
Abstracts and all correspondence should be sent to the Conference Office:
VI - The Association of Swedish Engineering Industries,
Storgatan 5, Box 5510, S-11485 Stockholm, Sweden.
Attention: Asa Midbeck Tel: +46 8 782 09 59 Fax: +46 8 782 09 00
Anders Marcelius Tel: +46 8 782 09 27 Fax: +46 8 782 08 64
Conference Cost: Participant cost of SEK 5500 will include documentation,
exhibition attendance, 3 days lunches, coffee twice a day, reception and
buffet at the City Hall Monday June 3rd evening, and the boat excursion
in the archipelago with dinner Tuesday June 4th.
Exhibition: Suppliers of materials, equipment, test and analysis
instruments, universities and research institutes are invited to
exhibit their products. There will be a SEK 6000 fee for an exhibition
place - please contact the Conference Office.
Technical Topics:
Physical properties, e.g. optical, electrical, thermal.
Design, simulation, modelling.
Reliability, life-expectancy, harsh testing, heat management.
Processing and application techniques.
Packaging and interconnection technology, e.g. flip-chip, optical, DCA,
BGA, TAB, COB, PTH, SMT, power components.
Environmental issues, e.g. life-cycle analysis, ecology & eco-toxicology.
Novel technologies.
Economic feasibilities.
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CALL FOR PAPERS
46th ECTC
Electronic Component and Technology Conference
May 28-31, 1996
Orlando, Forida: Buena Vista Palace
Abstracts of approximately 500 words are needed for proposed papers for ECTC.
New developments and knowledge in the following areas are invited.
* Components: New technologies, high frequency applciations,
usability and reliability (with special focus on
wireless, flat panel displays, and portable electronics).
* Connectors: Module socket, card edge, back panel, cable, low power
connectors with emphasis on high density and high
performance applications.
* Interconnections: First level, cost effective interconnection
technologies including TAB, wire, flip-chip,
and conductive polymers, bare chip attach to
glass, FR4 and flex for temporary and permanent
interconnections.
* Manufacturing Technology: JIT, SPC, robotics, design for
manufacturability, ISO cost identification and
control, manufacturing processes, yield, test,
manufacturing equipment.
* Materials and Processing: Polymerics, ceramics, metals, composites,
thermal display packaging materials: properties,
processing and interfaces.
* Modeling and Simulation: Electrical, thermal, optical and
mechanical modeling.
* Multichip Packaging: Design, fabrication, new technologies for
high density/high speed applications, known-good-die,
direct chip attach, MCM-C, MCM-D, MCM-L, 3-D, and
hybrid packaging (SMT, COB, thick and thin film).
* Opto-Electronics: Packaging for fiber-optic modules, infrared
wireless, consumer optoelectronics, flat-panel,
projection and micro-displays, optical amplifiers,
lasers, detectors, waveguides, OEICs, and passive
components.
POSTER PAPERS: Quality/reliability and single chip packaging
are of particular interest.
SEND ABSTRACT TO
Jim Billigmeier
3M Company
Bldg 201-1W-28, 1&C Sector Research Lab.
St Paul, MN 55144-1000
Tel: (612)733-3090
Fax: (612)737-5335
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Call For Papers
Multichip Module Test Advanced Technology Workshop
The Multichip Module Test Advanced Technology Workshop will explore
state-of-the-art MCM test concepts, trends, and practices. The
workshop focuses on test, diagnosis and repair challenges for multichip
modules (MCMs).
Topics for the MCM test workshop include design-for-testability, economics
and cost analysis, known-good die, MCM burn-in, module-level test, multichip
built-in self-test, repair and rework, substrate testing, test and
instrumentation, trouble shooting and diagnosis, and testing strategies.
To present recent developments at the workshop, submit an extended abstract
(one to three pages long) to
Janet Kingstom
ISHM
1850 Centennial Park Dr., Suite 105
Reston VA 22091
Tel: (703)758-1060
Fax: (703)758-1066
DEADLINE FOR RECEIPT OF SUBMISSIONS: Feb. 23, 1996.
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CHIPCON '96
First Int'l Conference on Chip Scale/Chip SIze Packaging Technology
Feb. 13, 1996
Sunnyvale, California
Sponsored by: Semiconductor Technology Center (STC)
Papaers will cover current, unpublished work in the area of
Chip Scale/Chip Size Packaging (CSP) Technology including design, processes,
materials, assembly, performance, reliability, cost and yield considerations,
trends, applications, encapsulation, thermal and electrical issues, testing
and burn-in, equipment and services, and repair and rework.
The Multichip Module Test Advanced Technology Workshop will explore
state-of-the-art MCM test concepts, trends, and practices. The
workshop focuses on test, diagnosis and repair challenges for multichip
modules (MCMs).
Topics for the MCM test workshop include design-for-testability, economics
and cost analysis, known-good die, MCM burn-in, module-level test, multichip
built-in self-test, repair and rework, substrate testing, test and
instrumentation, trouble shooting and diagnosis, and testing strategies.
For more information, contact
Subash Khadpe
Semiconductor Technology Center
PO Box 38
Neffs, PA 18065-0038
Tel: (610)799-0419
Fax: (610)799-0519
Email: skhadpe@aol.com
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ANNOUNCEMENT
PCB Design Conference
March 18-22, 1996
Santa Clara, California
The PCB design industry trives on change and challenge, and ongoing
education is one of the best ways to stay abreast of issues. Now in
its fifth year, the PCB Design Conference is the definitive resource
for education in the industry, helping the engineer stay at the forefront
pf printed circuit board design technology.
The conference provides nine full day tutorials and fifty presentations (in
three strategic tracks).
For further information, contact
PCB Design Conference
c/o ARI
1420 MacArthur Dr. #104
Carrollton, TX 75005
Tel: (214)323-0575
Fax: (214)245-8700
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SHORT COURSES
Short Course
MULTICHIP MODULE PACKAGING TECHNOLOGY
Sunday May 5, 1996
9:00 AM until 4:30 PM
189th Meeting of the Electrochemical Society
Los Angeles, California
Submitted by W. D. Brown"
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The packaging buzz word for the 90's is multichip modules (MCMs).
A multichip module is an electronic package structure consisting of two or
more "bare" or unpackaged integrated circuits interconnected on a common
substrate. The interconnects are usually multiple layers, separated by
insulating material, and interconnected by conductive vias. The MCM
market is expected to grow at a compound annual growtha rate of 60% to more
than $20b/year in the year 2000 [1]. MCMs have been around for a long
time, although not in the same form as seen today. Wiring densities of
up to 90% are possible with MCMs, as compared to only about 10% for
conventional printed circuit boards.
A multichip module is a highly functional module of several integrated
circuits or a printed circuit board. In fact, the major driving force
behind MCMs is the need to miniaturize and improve the performance of the
conventional printed circuit board. MCMs offer better performance
density per unit cost than conventional single-chip packages on printed
ciruit boards. As workstations approach the performance of mainframe
computers, and personal computers and laptop computers approach
workstations, the need to reduce wiring delay by eliminating individually
packaged chips is obvious. Signal delay is minimized in MCMs due to a
reduction in total length of the interconnect which, in turn, reduces
parasitic circuit elements.
Depending on the supporting substrate, MCMs can be classified as
MCM-L (laminate), MCM-C (ceramic), or MCM-D (deposited). MCM-Ls use
advanced printed circuit board technologies, copper conductors, and
plastic laminate-based dielectrics. The major advantage of MCM-Ls is low
cost as a result of an existing infrastructure for high volume
production. However, MCM-Ls have low routing density, poor thermal
conductivity through the substrate, a high coefficient of thermal
expansion, high crosstalk, and moisture sensitivity. MCM-Cs use
thick-film or screen printing technologies on cofired ceramic
substrates. The typical linewidth in MCM-Cs is 100 microns. A 64-layer
MCM-C, better known as the Thermal Conduction Module )TCM), is being used
in IBM mainframe computers. The interconnects on MCM-Ds are fabricated
by thin-film deposition of metals on deposited dielectrics of
polymer or inorganic dielectrics on silicon substrates. As such, very
fine features are possible in MCM-Ds. MCM-Ds permit the use of flipchip
technology which provides a unique interconnect structure that reduces
the substrate area.
This course will present an overview of multichip module technologies.
The packaging tradeoffs are first discussed. These tradeoffs must be
made at the system conceptual design stage, before any hardware is
fabricated or even designed in detail. Yet, the decision made at this
stage will determine the success or failure of the implementation of an
MCM. Next, the driving force behind and evolution of MCM technologies
will be presented. As will be shown, MCM technology evolves from
conventional printed circuit board technology, and yet, significant
difference exist between MCMs and PCBs. Different classes of MCMs, such
as MCM-L, MCM-C, and MCM-D, will be presented along with their
fabrication technologies. The course duration is estimated to be about 6
hours.
This short course is targeted at technologists, managers, and
engineers in the electronics and semiconductor industries who would like
to stay abreast of the new multichip module packaging technology. An
elementary knowledge of semiconductor processing technology is
recommended, but is not essential.
Instructor: Dr. Simon S. Ang
Department of Electrical Engineering
University of Arkansas
3217 Bell Engineering Center
Fayetteville, Arkansas 72701
Notes for the course are provided at the time of the course. The
registration fee for the course is $300.00 for Electrochemical Society
Members and $375.00 for Nonmembers. These fees cover the course,
luncheon, coffee breaks, and text materials. Students are offered a 50%
discount on course registration.
Further information about this course can be obtained from the
Electrochemical Society Headquarters at phone#: 609-737-1902; Fax#:
609-737-2743; E-mail: ecs@electrochem.org
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SHORT CONFERENCE/MEETING NOTICES
- Dec 4-6, 1995:
- Process Control of Solder Past: Using AC Electrical
Techniques.
Place: Indianaopolis, IN USA.
Contact: Michael Farmer, Marquette University (414)288-6360
- Dec. 11-12, 1995:
- SMTA Academy.
Place: Tempe, Arizona, USA.
Contact: SMTA (612)920-7682
- Feb. 13-16, 1996:
- 1996 International Flip Chip, Ball Grid Array,
TAB & Advanced Packaging Symposium (ITAP96)
Place: Northern California, USA.
Contact: Semiconductor Technology Center (610)799-0419
- March 3-7, 1996:
- IPC Printed Circuits Expo
Place: San Jose, California, USA.
Contact: IPC (708)509-9700
- March 6-8, 1996:
- 2nd International Packaging Materials Conference
Place: Atlanta, Georgia, USA.
Contact: Rajen Chanchani (505)844-3482
- April 5-7, 1996:
- IEEE Multichip Module Conference
Place: Santa Cruz, California, USA.
Contact: David Tuckerman (409)945-0151
- April 16-19, 1996:
- International Conference on MCMs
Place: Denver, Colorado, USA.
Contact: ISHM (703)758-1060
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COMPANY INFORMATION
INTERNATIONAL ANALYTICS CO. PO Box 2051,
Huntsville, AL 35804-2051, (205) 539-8118
Submitted by: Ronald Schmitz
Approximately two years ago, work on the PCB Reliability Assessment Code
(PRAC) was begun under and SBIR contract with Rome Labs, COTR, Peter Rocci.
The PRAC has now been completed. Beta testing ended in December of 1994,
and we began shipping in February of 1995.
PRAC is a program designed to perform PCB Reliability Assessment. It has
been developed as a series of analytical modules which operate in a PC,
MS-Windows environment. The modules can be used separately or together to
assess the effect that thermal and structural loads have on the life of
electronic components, component leads and solder joints. The code predicts
low cycle fatigue of components using Engelmaiers approach for SMT, and S-N
curves for PTH components. It also predicts high cycle fatigue using
Steinbergs approach for both SMT and PTH components. Extensive component and
material libraries are provided. Effort is currently underway to develop
interfaces to PCB CAD systems (e.g., P-CAD, TANGO, PADS and AutoCad).
More information can be found on our Web Homepage: http://ro.com/~prac/
To receive A FREE 30 Day Evaluation Copy of PRAC, please Email your request
to:
Ronald P. Schmitz
Product Development & Sales
International Analytics Co.
PO Box 2051, Huntsville, AL 35804-2051
Tel: (205) 539-8118
email: prac@ro.com
Commonly Asked Questions:
Q. What is PRAC?
A. PCB reliability assessment code that will identify potential
structural and thermal failures before you build your first board.
Q. What are the computer requirements?
A. Personal computer operating MS Windows with 4 MB RAM and a
VGA or SVGA monitor.
Q. How about cost?
A. Competitively priced at $1,495. Ask about discounts!
Q. Is it difficult to use?
A. The graphical interface is combined with extensive material and
component libraries. A cinch to use without reading the manual.
Q. What will it do for me?
A. Predicts component lead wire forces, moments and stresses, solder
forces and stresses, board stress and component life for thermal,
harmonic, random and shock loads.
Q. How long does it take to get answers?
A. A typical structural analysis takes 10 to 20 seconds.
A typical thermal analysis takes 10 to 60 seconds.
Q. Can I try it out before buying?
A. Yes! we offer a free 30-day trial.
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IEEE CPMT INFORMATION
Submitted by Paul Wesling:
The Table of Contents for upcoming/current issues of the IEEE Trans.
on Advanced Packaging can be browsed, to see what topics and papers
are being included. For example, the May issue of this quarterly
journal has a special section of six papers on the topic of
optoelectronics packaging, edited by R. Boudreau, and a second section
of 6 papers on Adhesive Joining Technology in Electronics Manufacturing,
edited by J. Morris. There are other sections on flip-chip packaging,
multichip modules, electrical performance modeling, and other topics in
this issue.
To browse the Table of Contents, access the WEB server at
http://www.ieee.org/pub_preview/cpmtb_toc.html
Each quarter, this location will be updated with the next Table of Contents.
For information on subscribing to this quarterly journal (800 pages/year;
about 100 papers), call IEEE (in the USA tollfree at 1-800-678-IEEE) and
ask for publication 021-1651. Subscriptions are $250/year (non-IEEE
members). You may wish to join IEEE (members get substantial discounts);
if so, request information from IEEE or contact p.wesling@ieee.org for
information.
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