CPMT INFORMATION
CONFERENCES AND WORKSHOPS
OSA Spring Topical Meeting on Optics in Computing - OC97
Hyatt Lake Tahoe, Incline Village NV
March 17-21 1997
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Sponsored by: Optical Society of America (OSA)
In cooperation with: SPIE
Submitted by: Kelvin Wagner
Web site: http://w3.osa.org/mtg_conf/topicals/spring97/000C.htm
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SCOPE
The sixth OSA Topical Meeting on Optics in Computing (formerly
Optical Computing) explores the applications of optics in computing,
interconnections, and information processing with invited and
contributed oral presentations and posters. Papers are solicited in
all applications of optics to computing and processing. Germane topics
include optical interconnections within electronic computers, system
demonstrations of digital optical computing, optical neural networks,
optical signal processing and novel optical processing architectures,
development of active and passive components for novel computing
systems, and progress in techniques and subsystems such as optical
interconnections, optical memory, and optical logic.
LIST OF TOPICS:
Optical computing architectures and algorithms
Optical computing system demonstrations
Optical interconnects for electronic computers
Adaptive optical signal processing
Parallel access optical memory
Optical neural networks and learning systems
Optomechanics, packaging, and miniaturization of optical and
optoelectronic computers
Massively parallel optical interconnections, static and reconfigurable
Novel optical image processing
Optical encryption and authentication
Optical Implementation of novel computer architectures
Wavelength domain parallelism
3D optoelectronic systems
Optical backplanes
Optoelectronic devices enabling optical computing systems
Nonlinear optical phenomena for logic gates
Novel nonlinear optical, electro-optic, acousto-optic, and
photorefractive components for optical computing systems
Optical conversions between time, wavelength and space domain
parallelism
Optical and holographic components for optical computing systems
Fundamental physical limits of optical computing components and
systems
PRELIMINARY LIST OF INVITED AND PLENARY SPEAKERS:
Holographic Storage Applications,Demetri Psaltis, California Institute
of Technology
Alternatives and imperatives for optical interconnect in high
performance computers, Burton Smith, Tera Computer
Medical and Synthetic Aperture Microscope Image Reconstruction using
Opto-Electronic Processing,Terry Turpin, Essex Corporation
Title to be announced, Steve Benton, MIT Media Laboratory
Title to be announced, Dan Dapkus, University of Southern California
2D coding and signal processing for volume memory interfaces, Mark
Neifeld, University of Arizona
Constructing a Free-Space Optical Backplane: Challenges and Choices,
David Plant, McGill University, Canada
Co-located meetings:
Spatial Light Modulators,
Ultrafast Electronics and Optoelectronics,
Quantum Optoelectronics
Optics in Computing Technical Program Committee
Kelvin Wagner, University of Colorado, General Chair
Matthew Derstine, Optivision Inc., Program Chair
Karl-Heinz Brenner, University of Mannheim, Germany
Pierre Chavel, Institut d'Optique, France
Neil Collings, University of Neuchatel, Switzerland
Alan Craig, Air Force Office of Scientific Research
Joseph W. Goodman, Stanford University
Peter Guilfoyle, OptiComp Corp.
Mary Hibbs-Brenner, Honeywell Inc.
Mohammed Islam, University of Michigan
B. Keith Jenkins, University of Southern California
Fouad Kiamilev, University of North Carolina at Charlotte
Raymond K. Kostuk, University of Arizona
Takashi Kurokawa, NTT
Frederick McCormick, Call/Recall Inc.
Andrei Mikaelian, Institute of Optical Neural Technologies, Russian
Academy of Sciences
David A. B. Miller, Stanford University
John Pellegrino, Army Research Laboratory
Demetri Psaltis, California Insitute of Technology
Toshikazu Sakano, NTT, Japan
Marc Stiller, ROITech
Jun Tanida, University of Osaka, Japan
Frank Tooley, McGill University, Canada
Andrew Walker, Heriot-Watt University, U.K.
Toyohiko Yatagai, University of Tsukuba, Japan
For further information contact:
Optical Society of America
Conference Services
2010 Massachusetts Ave. NW
Washington DC 20036-1023
202-223-0920 (phone), 202-416-6100 (FAX)
Dr. Matt Derstine, Program Chair
Optivision
+1 415-855-1776 - derstine@portal.optivision.com
Prof. Kelvin Wagner, General Chair
University of Colorado, Boulder
+1 303-492-4661 - kelvin@optics.colorado.edu
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1997 International Symposium on Physical Design
Napa Valley, California
April 14-16, 1997
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Sponsored by: ACM SIGDA
In cooperation with: IEEE Circuits and Systems Society
Submitted by: 1997 International Symposium on Physical Design
Web site: http://www.cs.virginia.edu/~ispd97/
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SCOPE
The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems. All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium. Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop. Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings.
Topics of interest include but are not limited to:
1. Management of design data and constraints
2. Interactions with behavior-level synthesis flows
3. Interactions with logic-level (re-)synthesis flows
4. Analysis and management of power dissipation
5. Techniques for high-performance design
6. Floorplanning and building-block assembly
7. Estimation and point-tool modeling
8. Partitioning, placement and routing
9. Special structures for clock, power, or test
10. Compaction and layout verification
11. Performance analysis and physical verification
12. Physical design for manufacturability and yield
13. Mixed-signal and system-level issues.
IMPORTANT DATES:
Submission deadline: December 20, 1996
Acceptance notification: February 1, 1997
Camera-ready (6 page limit) due: March 1, 1997
SUBMISSION OF PAPERS:
Authors should submit full-length, original, unpublished papers
(maximum 20 pages double spaced) along with an abstract of at most
200 words and contact author information (name, street/mailing address,
telephone/fax, e-mail).
Electronic submission via uuencoded e-mail is encouraged (single
postscript file, formatted for 8 1/2" x 11" paper, compressed with
Unix "compress" or "gzip''). Email to:
ispd97@ece.nwu.edu
Alternatively, send ten (10) copies of the paper to:
Prof. Majid Sarrafzadeh
Technical Program Chair, ISPD-97
Dept. of ECE, Northwestern University
2145 Sheridan Road, Evanston, IL 60208 USA
Tel 847-491-7378 / Fax 847-467-4144
SYMPOSIUM INFORMATION:
To obtain information regarding the Symposium or to be added to the
Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu.
Information can also be found on the ISPD-97 web page:
http://www.cs.virginia.edu/~ispd97/
SYMPOSIUM ORGANIZATION:
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee: J. Cohoon (Virginia), S. Dasgupta
(Sematech), S. M. Kang (Illinois), B.
Preas (Xerox PARC)
Program Chair: M. Sarrafzadeh (Northwestern)
Keynote Address: T. C. Hu (UC San Diego) & E. S. Kuh (UC
Berkeley)
Special Address: R. Camposano (Synopsys)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
W. W.-M. Dai (UC Santa Cruz)
J. Frankle (Xilinx)
D. D. Hill (Synopsys)
M. A. B. Jackson (Motorola)
J. A. G. Jess (Eindhoven)
Y.-L. Lin (Tsing Hua)
C. L. Liu (Illinois)
M. Marek-Sadowska (UC Santa Barbara)
M. Sarrafzadeh (Northwestern)
C. Sechen (Washington)
K. Takamizawa (NEC)
M. Wiesel (Intel)
D. F. Wong (Texas-Austin)
E. Yoffa (IBM)
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SPECIAL SESSION ON
PARALLEL ALGORITHMS AND ARCHITECTURES FOR NEURAL PROCESSING
(part of the)
ICA3PP-97
The IEEE Third International Conference on
Algorithms and Architectures for Parallel Processing
Melbourne, Australia
December 8-12, 1997
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Sponsored by: IEEE Victoria Section, IEEE Computer Society, Deakin
University, Faculty of Science and Technology Deakin University.
Submitted by: Vincenzo Piuri
Web site: http://www.cm.deakin.edu.au/ica3pp97
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Conference Chairperson: A. Goscinski, Deakin University, Australia
Special Session Organizer: Prof. Vincenzo Piuri
Dept. Electronics and Information
Politecnico di Milano
piazza L. da Vinci 32
I-20133 Milano, Italy
phone +39-2-2399-3606 or 3623
fax +39-2-2399-3411
email piuri@elet.polimi.it
SCOPE
The ICA3PP-97 Conference is directed to bring together developers and
researchers from universities, industry and government to advance
science and technology in distributed and parallel systems and
processing.
The special session on "Parallel Algorithms and Architectures for
Neural Processing" will focus on the neural computation.
This class of parallel processing paradigms has been shown effective
to solve several difficult problems when an algorithmic approach is
not known or too complex or impossible. Major application areas
currently explored by reasearcher and practitioners are
identification, control, robotics, signal and image processing,
pattern classification, recognition, high-level vision, time series
analysis.
In many applications or in the case of real-time systems, the amount
of data that need to be processed is so high that carefully-tailored
neural paradigms and optimized parallel architecture are mandatory.
This special session will present and discuss both theoretical
aspects and architectural solutions for neural processing, in order
to provide the algorithmic and architectural frameworks for an
effective application of these parallel computation techniques.
TOPICS OF INTEREST
Contributions describing original research, surveys, theoretical
results, design methodologies and applications are solicited with
particular reference to, but not limited to, the following areas:
1. Algorithms: neural models, theoretical foundations, learning
techniques, configuration optimization, network minimization,
precision, sensitivity, generalization ability, design tools,
design methodologies.
2. Architectures: general-purpose computer/distributed software
implementation, massively-parallel computer software
implementation, programmable neural architectures, dedicated
architectures, technologies (analog VLSI, digital VLSI, WSI,
MCM, FPGA, optical, mixed), performance evaluation, interfacing,
on-line/on-board learning support, fault tolerance, hybrid
systems, embedded systems, heterogeneous systems, codesign,
high-level synthesis, design methodologies, design tools.
SUMMARY SUBMISSION
Perspective authors should submit 6 copies of an extended summary (at
least 5 pages plus figures and tables) or the full paper (not
exceeding 20 pages) to the special session organizer, Prof. Vincenzo
Piuri, by March 17, 1997. Submission should include authors' names,
affiliations, addresses, fax and phone numbers, email addresses, on
the cover page.
Submission implies the willingness of at least one of the authors to
register and present the paper, if accepted.
Notification of acceptance/rejection will be mailed by July 18, 1997.
Camera-ready papers are due by September 1, 1997.
FURTHER INFORMATION
Further information about the whole conference can be found at the WWW
site http://www.cm.deakin.edu.au/ica3pp97
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Special Sessions: INTERpack '97: (a)
Material and Interfacial Characterization and (b) Experimental Mechanics in
Packaging
Sessions on:
MATERIAL & INTERFACIAL CHARACTERIZATION
AND EXPERIMENTAL MECHANICS IN PACKAGING
at
INTERpack '97
Hotel Orchid at Mauna Lani, Kohala Coast
Island of Hawai'i, USA
June 15-19, 1997
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Submitted by: Koneru Ramakrishna
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SCOPE
MATERIAL CHARACTERIZATION: Thermo-mechanical, thermal and diffusion
properties of materials used in electronic packaging, such as
silicon, GaAS, plated copper, aluminum, solders, ceramics,
composites, dielectrics, mold compounds, die attach materials,
thin films (polyimides etc.), and underfill-encapsulants. Topics
include, but are not limited to, temperature dependent
stress-strain behavior, fatigue, creep, relaxation, thermal
expansion, cure shrinkage, thermal conductivity and specific heat,
etc. New and novel methods of material testing for electronic
packaging - package, sub-system and system level.
CHARACTERIZATION OF INTERFACES: Metal-metal, metal-dielectrics,
metal-polymers. Topics include measurement of and measurement
techniques for adhesion, delamination, interfacial crack
propagation, toughness of materials, and fracture and deformation,
pop-corn performance, diffusion of moisture in thermo-sets and
thermo-plastics of interest to packaging.
IN-SITU MEASUREMENTS: Novel methods used in understanding mechanical
origins of failure of packages during manufacture, assembly and
stress tests. They may be photo-elastic, holographic, and different
types of moire' interferometric measurements, mini-line methods in
product development, nano-indentation, experimental verification of
analytical and numerical stress analyses.
INFORMATION:
Dr. K. Ramakrishna
Advanced Interconnect Systems Laboratories
Motorola, Inc., MD: K-1
3501 Ed Bluestein Boulevard
Austin, TX 78721
Phone: (512) 933-8866
FAX: (512) 933-6344
email:rp2045@email.sps.mot.com
Dr. Bahgat G. Sammakia
E22G/257-3B, P.O. 8000
IBM Corporation
701 North Street
Endicott, NY 13760-8000
Phone: (607) 757-1072
FAX: (607) 757-1126
email:sammakia@endicott.vnet.ibm.com
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Second Workshop on Optics and Computer Science (WOCS)
Geneva, CH
April 1, 1997
(part of the)
11th International Parallel Processing Symposium (IPPS)
Geneva, CH
April 1-5, 1997
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Submitted by: wocs@ece.ucsd.edu
Web Sites:
WOCS workshop Web site: http://soliton.ucsd.edu/geneva
IPPS'97 Web site: http://cuiwww.unige.ch/~ipps97/
WOCS Inquiries: pmarchand@ucsd.edu or berthome@lri.fr
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Scope of the Workshop
Advances in semiconductor technologies coupled with progress in parallel
processing and multi-computing are placing stringent requirements on
inter-system and intra-system communications. Demands for high density,
high bandwidth, and low power interconnections are already present in a
wide variety of computing and switching applications, including, for
example, multiprocessing and parallel computing (simulations of real
problems, monitoring of parallel programming, etc), and enhanced digital
telecommunications services (broadcast TV, video on demand, video
conferencing, wireless communication, etc.). Furthermore, with advances
in silicon and Ga-As technologies, processor speed will soon reach the
gigahertz (GHz) range. Thus, the communication technology is becoming and
will remain a potential bottleneck in many systems. This dictates that
significant progress needs to be made in the traditional metal-based
interconnects, and/or that new interconnect technologies, such as
optics, be introduced in these systems.
Optical means are now widely used in telecommunication networks and the
evolution of optical and optoelectronic technologies tends to show that
they could be successfully introduced in shorter distance interconnection
systems such as parallel computers. These technologies offer a wide
range of techniques that can be used in interconnection systems. But
introducing optics in interconnect systems also means that specific
problems have yet to be solved while some unique features of the
technology must be taken into account in order to design optimal systems.
Such problems and features include device characteristics, network
topologies, packaging issues, compatibility with silicon processors,
system level modeling, etc ...
The purpose of this workshop is twofold. First, we hope to provide an
opportunity for the optical, architectural, and communications research
communities to get together for a fruitful exchange of ideas. The goal
is to bring optical interconnects research into the main stream of
research in parallel computing, while at the same time providing the
parallel computing community with a more comprehensive understanding of
the advantages and limitations of optics as applied to high-speed data
communication within digital systems. In addition, we intend to
assemble a group of major research contributors to the field of optical
interconnects in order to provide an overview of its current status,
and to identify future directions. By virtue of its location, this
workshop will provide an excellent opportunity for European researchers
to present their results in this field.
The workshop will feature invited speakers, several sessions of
contributed papers, and a panel discussion.
Important dates
Submission deadline .............. 30 November 1996
Notification of acceptance ....... 10 January 1997
Camera ready paper ............... 31 January 1997
Submission Guidelines
Authors are invited to submit manuscripts that demonstrate original
unpublished research in all areas of optical interconnections including
development of experimental or commercial systems. Topics of interest
include but are not limited to:
* High-Speed Interconnections
* Optical Interconnects
* Parallel Optical Architectures
* Reconfigurable Optical Interconnects and Architectures
* Applications of Optical interconnects
* Modeling of Optical Systems and Applications
* Performance Analysis and Comparisons
* Packaging of optical interconnects
* System Demonstrations
* Routing in Optical Networks
To submit an original research paper, send your complete manuscript (not
to exceed 12 single-spaced pages of text using point size 12 type on 8
1/2 X 11 inch or A4 pages) to the Program Chairs. References, figures,
tables, etc. must be included in the 12 pages. Electronic submissions are
encouraged and should be sent to pmarchand@ucsd.edu or berthome@lri.fr
Electronic submissions must be in the form of a readable postscript file
containing the following header information in ASCII form: title, author
name(s), abstract, postal address, e-mail address, and telephone and fax
numbers. The header (in ASCII) should be followed by the postscript
version of the complete manuscript (including title, author's name,
affiliation, and abstract).
All manuscripts will be reviewed. Manuscripts must be received by 30
November 1996. Notification of review decisions will be sent by 10
January 1997. Authors will receive, along with the notification of
acceptance, the IEEE author's kit for their papers. Camera-ready papers
are due 31 January 1997 to match IPPS deadlines. The proceedings will be
available at the Symposium and published by IEEE.
Hard copy submissions are also permitted and, like electronic
submissions, must be received by 30 November 1996. Send six copies of the
manuscript to:
Philippe J. Marchand or Pascal Berthome
University of California, San Diego Universite de Paris Sud
ECE Department LRI
9500 Gilman Drive Bat. 490
La Jolla CA 92093-0407 91405 Orsay Cedex
USA France
pmarchand@ucsd.edu berthome@lri.fr
Invited speakers
T. Drabik, Georgia Institute of Technology, Metz, France and Atlanta,
USA. "How can we make optical interconnects mundane?"
A. Ferreira, LIP, Lyon, France
"Towards effective models for OPS-based lightwave networks"
S. Levitan, University of Pittsburgh, Pittsburgh, USA
"Forging a computer aided design tool for digital optoelectronic
systems"
Steering Committee
Timothy Drabik, Georgia Institute of Technology, Metz, France and
Atlanta, USA
Sadik C. Esener, University of California, San Diego, USA
Afonso Ferreira, Laboratoire d'Informatique du Parallelisme, ENS Lyon,
France
Program Committee
Pascal Berthome, LRI, Universite de Paris Sud, France (Computer Science
Chair)
Philippe Marchand, University of California, San Diego, USA (Optics
Chair)
Dominique Barth, LRI, Orsay, France
Eric Belhaire, IEF, Orsay, France
Jean-Claude Bermond, I3S, Nice-Sophia Antipolis, France
Karl Heinz Brenner, Mannheim, Germany
Jacek Chrostowski, NRC, Ottawa, Canada
Marc Desmulliez, Herriot-Watt, Scotland
Ashok V. Krishnamoorthy, Lucent Bell-Labs, USA
Philippe Lalanne, IOTA, France
Ahmed Louri, University of Arizona, USA
Yao Li, NEC Research Institute, USA
Nicolas Mauduit, France
Frederick B. McCormick Jr., Call-Recall Inc., USA
M. Ajmone Marsan, Torino, Italy
Rami Melhem, University of Pittsburgh, USA
Haldun Ozaktas, Bilkent University, Turkey
Ramamohan Paturi, UCSD, USA
Larry Rudolph, MIT, USA.
Assaf Schuster, Technion, Israel
Ted Szymanski, McGill, Montreal, Canada
Jun Tanida, Osaka University, Japan
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The PACIFIC RIM / ASME International, Intersociety
Electronic & Photonic Packaging Conference
(INTERpack '97)
Hotel Orchid at Mauna Lani
Kohala Coast, Island of Hawai'i, USA
June 15-19, 1997
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Sponsored by: The American Society of Mechanical Engineers International
(ASME)
Participating Organizations:
The Japan Society of Mechanical Engineers (JSME)
The Institute of Electrical & Electronics Engineers (IEEE)
International Electronic Packaging Society (IEPS)
The International Society for Hybrid Microelectronics (ISHM)
Society of Plastics Engineers (SPE)
Optical Society of America (OSA)
Materials Research Society (MRS)
Japan Welding Society (JWS)
Japan Institute for Interconnecting and Packaging Electronic Circuits
(JIIPEC)
The Institute of Electronics Information and Communication Engineers
(IEICE)
SHM-The Microelectronics Society JAPAN
The Japan Society for Composite Materials (JSCM)
Japanese Society for Strength and Fracture of Materials (JSSFM)
The Japanese Society for Non-Destructive Inspection (JSNI)
Society of Automotive Engineers of Japan, Inc. (SAEJ)
The Society of Naval Architects of Japan (SNAJ)
Submitted by: "D.C.Whalley"
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CONFERENCE OBJECTIVES
International cooperations, understanding and promotion of efforts and
disciplines in Microelectronics, Optoelectronics, and Photonics Packaging
Engineering in an East/West business setting. Dissemination of knowledge
pertaining to the art, science and practice in Electronic and Photonic
Packaging Engineering will serve as the foundation upon which the
conference program will be developed.
COMMITTEES
Advisory Committee: A. Bar-Cohen, T.R. Hsu, A.D. Kraus, S. Matsuoka, W.
Nakayama
General Chairs: E. Suhir (US), M. Shiratori (Japan)
Program Chairs: Y.-C. Lee (US), G. Subbarayan (US)
International Liasons: H. Abe, I. Ikegami (Japan); Y.-H. Hung, A. Lin
(Taiwan); K.W. Paik (Korea); M. Sceats (Australia); A. Tay
(Singapore); A. Tylikowski (Poland), D. Whalley (UK); E. Zakel
(Germany), Johan Liu (Sweden).
Program Committee: includes the international liasons and other leading
specialists in the field.
KEYNOTE SPEAKERS
R. Hanneman (US), J. Hwang (US), F. Ishitsuka (Japan), M. Pecht (US), R.
Tummala (US)
INVITED SPEAKERS
Partial list of invited speakers includes: H. Abe (Japan), D. Agonafer
(US), P. Ayyaswami (US), A. Bar-Cohen (US), W.T. Chen (US), H. Conrad
(US), R. Darveaux, (US), C. S. Desai (US), P. Engel (US), J. Fillo (US),
D. Frear (US), L. Goldmann(US), G. Grimes (US), C. Handwerker (US), P.
Haugsjaa (US), Y. Hiruta(Japan), W.K. Jones (US), N. Koopman (US), J. Lau
(US), C.K. Lim (US), A.Lin (Taiwan), R. Mahajan (US), S. Matsuoka (US),
L.L. Moresco (US), L.Nguyen (US), W. Nakayama (Japan), S.-Y. Oh (Korea),
Y. Pao (US), R.Pryputniewicz (US), B.G. Sammakia (US), M. Sceats
(Australia), M. Shiratori (Japan), T. Suga (Japan), E. Suhir (US), A.A.
Tay (Singapore), Y. Tsukada (Japan), E. Zakel (Germany), D.J. Williams
(UK), C.P. Wong (US).
WHO SHOULD ATTEND?
Researchers, designers, technical managers, electronic and photonic
packaging system developers and users involved in Microelectronic and
Photonic Packaging. The technical program will have strong technical
content and will include panel sessions, paper presentations and short
courses (tutorials) addressing both fundamental and applied aspects of
the "high technology" engineering as related to the field of packaging.
Paper presentations will be published in the conference proceedings. The
mix of speakers, geographical origins and technical backgrounds will be
very broad. Particular emphasis will be placed on East/West technology
transfer and mutually beneficial business opportunities/ applications
contained within a cooperative international electronic packaging
industry environment.
TUTORIALS
Inter-society sponsored tutorials will be featured as part of the
INTERpack '97 program. Each tutorial will focus on technology transfer
and the associated business opportunities present within research &
development, manufacturing & application of Electronic & Photonic
Packaging.
PUBLICATIONS
As a joint, East/West Inter-society publications event, INTERpack '97
will also feature the latest in Electronic & Photonic Packaging
publications and supporting materials on topics such as Microelectronics,
Optoelectronics & Photonics Packaging engineering.
EXHIBITION
Industrial/research exhibits featuring both Pacific Rim and Western
products/technologies will be open to all conference participants.
To be included in the conference as an exhibitor or to receive further
details regarding these and other yet-to-be announced INTERpack '97
special program features, please complete the Intent to Participate form
and return to the address listed. You and/or your organization will be
contacted.
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The Seventh Great Lakes Symposium on VLSI (GLS-VLSI'97)
Urbana, Illinois, USA
March 13-15, 1997
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Submitted by: Rajesh Gupta
Web Site: http://www.ece.uiuc.edu/~vlsi97
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BACKGROUND
GLS-VLSI'97 is seventh in a series of symposiums exploring the recent
progress in VLSI circuits and systems design. The Seventh Great Lakes
Symposium will be hosted by University of Illinois at Urbana-Champaign
in conjunction with celebrations for CyberFest'97. The symposium
addresses all aspects of design, test and validation of
micro-electronics based systems. Original and unpublished articles are
invited.
REPRESENTATIVE TOPICS
Physical Design
Logic Synthesis & Verification
Testing, Design for Testability
Design and Tools for Low Power
Architectural-level Synthesis
Hardware/Software Co-design
Embedded Software, Code Generation.
Field-Programmable Gate Arrays
Multichip Modules
Specialized VLSI Architectures
Deep Sub-Micron VLSI Design
Applications.
Program Information
Professor Farid Najm, GLS-VLSI'97
209 C&SRL University of Illinois
1308 W. Main St.
Urbana, Illinois 61801.
Organizing Committee:
General Co-Chair: Steve (Sung-Mo) Kang, C. L. Liu, UIUC
Program Chair: Farid Najm, UIUC
Local Arrangements: Naresh Shanbhag, UIUC
Publicity: Rajesh K. Gupta, UC Irvine
Steering Committee & Industrial Liason: Naveed Sherwani, Intel
Corporation
Past Chair: Liang-Fang Chao, Iowa State
Technical Program Committee
Jacob Abraham, UT Austin
Vishwani Agrawal, AT&T
Magdy Bayoumi, SW Lousiana
S. Chakravarty, SUNY Buffalo
Enrico Macii, Poli. Torino
Miodrag Potkonjak, UCLA
Robert M. Owens, Penn State
Chris Papachristou, Case Western
Irith Pomeranz, U of Iowa
Gabriel Robins, U of Virginia
Edwin Sha, Notre Dame
S. Mohan, Xilinx
D. F. Wong, UT Austin
Yu Hen Hu, U of Wisconsin
M. Papaefthymiou, Yale
Xiaoqing Wen, Akita Univ.
Steve Bass, Notre Dame
Prith Banerjee, Northwestern U.
M. Sarrafzadeh, Northwestern U.
Steve Nowick, Columbia
Dontella Sciuto, Poli. Milano
Scott Hauck, Northwestern U.
Sharon Hu, Western Michigan
Hiroto Yasuura, Kyushu Univ.
Ibrahim Hajj, UIUC
Sofiene Tahar, Concordia Univ.
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MASSIVELY PARALLEL PROCESSING USING OPTICAL INTERCONNECTIONS
(MPPOI'97)
The Le Centre Sheraton Hotel
Montreal, Canada
June 22-24, 1997
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Sponsored by:IEEE CS TCCA (Technical Committee on Computer Architecture)
In cooperation with
ACM Special Interest Group on Architecture (SIGARCH)
The IEEE Lasers and Electro-optics Society (LEOS)
The Optical Society of America (OSA)
The International Society for Optical Engineering (SPIE)
Submitted by: Eugen Schenfeld
Web Site: http://www.cs.virginia.edu/~ispd97/
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BACKGROUND
The fourth annual conference on Massively Parallel Processing
Architectures using Optical Interconnections (MPPOI'97) will be held
on June 22-24, 1997 in the Le Centre Sheraton Hotel, Montreal, Canada.
The Conference will focus on the potential for using optical
interconnections in massively parallel processing systems, and their
effect on system and algorithm design.
Optics offer many benefits for interconnecting large numbers of
processing elements, but may require us to rethink how we build
parallel computer systems and communication networks, and how we write
applications. Fully exploring the capabilities of optical
interconnection networks requires an interdisciplinary effort. It is
critical that researchers in all areas of the field are aware of each
other's work and results. The intent of MPPOI is to assemble the
leading researchers and to build towards a synergetic approach to MPP
architectures, optical interconnections, operating systems, and
software development. The conference will feature invited speakers,
followed by several sessions of submitted papers, and will conclude
with a panel discussion.
TOPICS OF INTEREST include but are not limited to the following:
- Optical interconnections, Reconfigurable Architectures,
- Embedding and mapping of applications and algorithms,
- Packaging and layout of optical interconnections,
- Electro-optical, and opto-electronic components,
- Relative merits of optical technologies (free-space, fibers, wave
guides),
- Passive optical elements, Algorithms and applications exploiting,
- Data distribution and partitioning,
- Characterizing parallel applications,
- Cost/performance studies.
MANUSCRIPT SUBMISSION
Authors are invited to submit manuscripts which demonstrate original
unpublished research in areas of computer architecture and optical
interconnections. Papers submitted MUST NOT BE UNDER CONSIDERATIONS
FOR ANOTHER CONFERENCE or JOURNAL.
Authors are invited to submit manuscripts which demonstrate original
unpublished research in the above areas. Papers submitted must not be
under considerations for another conference. Send eight (8) copies of
the complete paper (not to exceed 15 single spaced, single sided pages)
to:
Dr. Eugen Schenfeld
MPPOI'97 Conference
NEC Research Institute,
4 Independence Way
Princeton, NJ 08540, USA
Tel: (609)951-2742,
Fax: (609)951-2482
email: MPPOI@RESEARCH.NJ.NEC.COM.
FAX OR ELECTRONIC SUBMISSIONS WILL NOT BE CONSIDERED.
The proceedings will be published by the IEEE CS Press and will be
available at the conference.
DEADLINE
MANUSCRIPTS MUST BE RECEIVED BY January 31, 1997 (HARD DEADLINE).
Notification of review decisions will be mailed by March 14, 1997.
Camera ready papers due at IEEE CS Press: April 30, 1997 (HARD DEADLINE)
NO EXTENSIONS WILL BE GIVEN TO THE ABOVE SUBMISSION DATES.
CONFERENCE CHAIR: Joseph W. Goodman, Stanford University
PROGRAM CO-CHAIRS
H. Scott Hinton, University of Colorado (Boulder)
Timothy M. Pinkston, USC
PUBLICITY and PUBLICATION CHAIR
Eugen Schenfeld, NEC Research Institute
PROGRAM COMMITTEE
J. Chrowtowski, NRC (Canada)
J. Duato, University of Valencia (Spain)
A. Ferreira, CNRS, LIP - ENS Lyon (France)
E. Frietman, Delft University (Holland)
K. Ghose, SUNY Binghamton (USA)
M. Haney, George Mason University (USA)
K. Hwang, Hong Kong University (USA)
M. Ishikawa, University of Tokyo (Japan)
N. Jokerst, Georgia Tech., (USA)
K. Kasahara, NEC Corp. (Japan)
F. Kiamilev, University of N. Carolina, Charlotte (USA)
R. Kostuk, University of Arizona (USA)
C. Kuznia, USC (USA)
A. Krishnamoorthy, Lucent Technologies (USA)
A. Lentine, Lucent Technologies (USA)
A. Louri, University of Arizona (USA)
F. McCormick, UCSD (USA)
J. Midwinter, University College London (UK)
D. A. B. Miller, Stanford University (USA)
L. Ni, Michigan State University (USA)
A. Nowatzyk, Sun Microsystems (USA)
D. Panda, Ohio State University (USA)
D. Plant, McGill University (Canada)
J. Rowlette, AMP (USA)
A. Sawchuk, USC (USA)
S. Scott, Cray Research (USA)
B. Shoop, US Military Academy (USA)
C. Stunkel, IBM T.J. Watson Research
H. Thienpont, Vrue Universiteit Brussel, (Belgium)
F. Tooley, McGill University, (Canada)
A. Walker, Heriot-Watt University (UK)
D. S. Wills, Georgia Tech. (USA)
H. Wilmsen, Nortel (Canada)
S. Yalamanchili, Georgia Tech. (USA)
T. Szymanski, McGill University (Canada)
Return to Index
Return to Conference Listing
8th Annual Workshop on Interconnections within
High-Speed Digital Systems
Santa Fe, NM
May 11-14, 1997
---------------------------------------------------
Submitted by: Philippe J. Marchand
Web Site: http://soliton.ucsd.edu/ihsds/santafe97/
---------------------------------------------------
SCOPE OF THE WORKSHOP
The continuing rapid increase in the performance of high speed
electronics and communications technology has led to dramatic
improvements in advanced computing and communications systems. The rapid
growth of computer internetworking and the rise of new applications
such as multimedia and virtual reality are driving the requirements for
still higher levels of computing and communications performance.
Interconnections within digital computing and switching systems today
are often a performance bottleneck. The purpose of this Workshop is to
determine the interconnection requirements of emerging and future
computer and communications systems, to disseminate information about
optical and electrical interconnection technology at the component,
packaging, and sub-systems level as well as issues related to the
implementation of these and their systems level impacts.
Because of the multi-disciplinary nature of these problems, this
Workshop brings together researchers and engineers with expertise in a
variety of fields including electronic, optoelectronic, and optical
interconnection technologies, advanced systems architectures as well as
the systems level perspective of algorithms and applications. The
Workshop is highly interactive - in addition to the tutorials and
invited talks, all attendees participate in smaller working groups to
discuss and address central focus Workshop problems.
1997 WORKING GROUP DESIGN PROBLEM
The 1997 problem will be to design an immersive Virtual Reality system
capable of hosting two human participants, and one teleoperated robot,
in a simulation environment rich enough to be useful for practicing
"real world" tasks.
CALL FOR PAPERS
The Program Committee of the 1997 Workshop on Interconnects within
High-Speed Digital Systems is pleased to announce that it will accept
contributed papers on topics of interest to the interconnect community.
While the traditional emphasis of the workshop on
working group activities and invited talks will be retained, it is the
belief of the committee that adding contributed papers will increase the
quality of the workshop experience by providing an alternative channel
for communicating new and important results.
Working groups are diverse and multi-disciplinary, and have considered
problems ranging from high-performance workstation design to
tele-medicine applications. Historically, this workshop has provided a
stimulating, highly interactive environment conducive to
thought-provoking discussion, with invited talks and keynote speakers of
the highest caliber. Take advantage of this opportunity to contribute
to a great Santa Fe experience!
Area of Interest
Submissions should be synergistic with the interests of the workshop,
and should focus on applications of high-speed interconnect, or on
individual technologies that relate to interconnection problems in
digital systems. A wide range of technologies are of interest including,
for example, multi-chip modules, parallel-optical data links, integrated
optoelectronics, high-speed electronics, optical and electronic
connector, cable, and packaging design,. Both electronic and optical
technologies are considered. Applications should share a need for
leading-edge interconnect technology. Areas as diverse as remote
surgery, gigabit networking, high-speed workstation design, cache-memory
subsystems, video-on-demand, and emerging interconnect protocols and
standards have been presented in the past. If your application or
technology fits within the workshop scope, we invite you to submit a
paper.
Instructions for Preparation of Abstract
Authors should provide an abstract and a summary of their results. The
abstract should not exceed 40 words, and should be provided on a single
page containing the title of the presentation, the name(s) of the
author(s), and a complete correspondence address, including FAX and
electronic mail. A separate, two-page summary of your topic should also
be submitted. The summary should be prepared in a camera-ready format
and must not exceed 2 standard pages (8.5 x 11 in or A4) with type size
of at least 10 pt. and 1 inch (25 mm) margins on all sides, and should
also contain the title, author name(s), and affiliation(s). All figures
and text must fit within the 2-page summary, which will form the basis
for committee decisions. For accepted papers, the abstracts will be
printed in the advance program, and the summaries will be distributed to
workshop participants. It is assumed that presenters have obtained all
permissions necessary to present their materials at this international
forum.
Send completed submissions to:
1997 Santa Fe Workshop
IEEE/LEOS Conference Services
P. O. Box 1331
445 Hoe's Lane
Piscataway, NJ 08855
Attn: Elsie Vega
Electronic submissions may be made to e.vega@ieee.org as a
Postscript(tm) file. Please make every effort to ensure the
compatibility of your files before sending them. If we can't print them,
we can't score them.
DEADLINE
Submissions must arrive at the IEEE no later than 3 PM Tuesday Nov. 26,
1996
WORKSHOP COMMITTEE
Workshop Chair
Frederick B. McCormick Jr., University of California San Diego and
Call/Recall Inc, San Diego, CA.
Program Chair
Ashok V. Krishnamoorthy, Lucent Bell-Labs, Holmdel, NJ.
Tutorials Chair
Craig Lund, Mercury Computer Systems.
Program Committee
Bruce Booth, Dupont, Wilmington, DE
Drew Doblar, Sun Microsystems, Mountain View, CA
Ireena Erteza, Sandia National Laboratories, Albuquerque, NM
Tulin Mangir, TM Associates, Santa Monica, CA
Ted K. Woodward, Lucent Bell-labs, Holmdel, NJ.
Working Group Chair
Howard Davidson, Sun Microsystems, Moutain View, CA.
Working Group Committee
Winston Chan, University of Iowa, Iowa City, IA.
Joseph E. Ford, Lucent Bell-Labs, Holmdel NJ.
Marc Christensen, George Mason University, Fairfax, VA.
Antonio Mendez, Mendez & Associates, Los Angeles, CA.
Andreas Nowatyzk, Sun Microsystems, Mountain View, CA
George Papen, University of Illinois, IL.
Publicity Chair
Philippe J. Marchand, University of California San Diego and
Parallel Solutions Inc, San Diego, CA.
Local Arrangements Chair
Richard Carson, Sandia National Labs, Albuquerque, NM.
Meeting Coordinator
Elsie Vega, IEEE/LEOS Meeting Manager
Steering Committee
Matthew Goodman, Bellcore, Red Bank, NJ
Mike Haney, George Mason University, Fairfax, VA
Tony Ticknor, Akzo Nocel Eletronic Systems, Sunnyvale, CA
International Liaisons
Toshikazu Sakano, NTT Optical Network Systems Laboratory, Kanagawa,
Japan Osamu Wada, Femtosecond Technology Research Association,
Kanagawa, Japan Arne Wallers, Ericsson Telecom AB, Stockholm, Sweden
MAILING LIST:
If you want to be added on the mailing list to receive the
advance program, please contact:
Elsie L. Vega
IEEE/LEOS Meetings Coordinator
445 Hoes Lane, PO Box 1331
Piscataway NJ 08855-1331
Phone: 908-562-3897
Fax: 908-562-8434
Email: e.vega@ieee.org
Return to Index
Return to Conference Listing
SEVENTH INTERNATIONAL SYMPOSIUM ON IC TECHNOLOGY,
SYSTEMS & APPLICATIONS
ISIC-97
Hyatt Regency, Singapore
September 10-12, 1997
---------------------------------------------------
Organized by: School of Electrical & Electronic Engineering,
Nanyang Technological University, Singapore
Sponsored by:
Lucent Technologies, Bell Labs Innovations
IEEE Singapore Section
IEE
Submitted by: ISIC97@ntuvax.ntu.ac.sg
---------------------------------------------------
BACKGROUND
The Seventh International Symposium on IC Technology,
Systems and Applications, ISIC-97, will be held on 10-12
September 1997. This symposium will provide a forum for
IC designers and manufacturing engineers, as well as
academics to present and share new research and development
results, techniques and problems. ISIC-97 coincides with
the 50th anniversary of the invention of TRANSISTOR. To
celebrate this occasion, the symposium will be highlighted
by the keynote address on "The Invention of the transistor
and other key advances" given by the President of Lucent
Technologies, Dan Stanzione and on "Implications for the
Future of Information Management" given by the Nobel
Laureate, Arno Penzias. Other renowned figures will also be
invited as guest speakers.
TOPICS OF INTEREST include but are not limited to the following:
A. DEVICE & IC TECHNOLOGY
1. Compound Semiconductor Devices
2. SOI
3. Testing and Yield Enhancement
4. Process Simulation
5. Device Physics and Modeling
6. Scaling of Devices and Technologies
7. New Processes and Materials
8. Reliability and Failure Analysis
9. Assembly and Packaging
B. INTEGRATED CIRCUITS AND SYSTEMS
1. Artificial Neural Networks and Fuzzy Logic
2. Fault-Tolerant Circuits
3. Circuit Design and Architecture
4. Timing and Communications
5. IC Sensors and MEMs
6. Switched Capacitor and Current Mode Circuits
7. Multiple-Valued Logic Circuits
8. BiCMOS Circuits
9. Low-Power Low-Voltage IC designs
10.Memories
11.Mixed-Signal Circuits and Systems
C. DESIGN AUTOMATION
1. Logic and System Synthesis
2. Simulation, Verification and Testability
3. Performance Optimization Methods
4. AI Methodology
5. Physical Design and Back Annotation
6. Innovative Design Capture Techniques
7. High Level Description Language
8. MCM Layout
D. APPLICATIONS
1. Audio, Electroacoustics and Video
2. Military Applications
3. Cellular Mobile Communications
4. Switched Mode Power Supplies
5. Broadband Communication Applications
E. SIGNAL PROCESSING
1. Speech and Image Processing
2. Multi-Dimensional Signal Processing
3. Wavelet Theory & Applications
4. Acoustic Signal Processing
5. Adaptive and Nonlinear Filtering
6. Multimedia
7. Specialized Signal Processors
TUTORIAL SESSIONS
Tutorial sessions on "RF IC Design and Systems" and
"DSP IC Design" are planned on the first day of the
symposium. Invitations are solicited for more tutorial
topics of current interest. Participants who wish to
contribute by giving tutorial sessions may submit proposals
to the Organizing Committee. Proposed topics of sufficient
interest among the delegates will be considered for the
tutorials.
EXHIBITION
An exhibition of relevant industrial equipment and systems
will be held in conjunction with the regular sessions for
paper presentations on the second and third day of the
conference.
REGISTRATION FEE
Conference
Early Bird: S$500 (payment before 15 June 1997)
Normal : S$600 (payment after 15 June 1997)
(fee inclusive of conference proceedings, tea-breaks, lunches,
banquet and 3% GST)
Tutorials
S$200 (payment made by 15 June 1997)
(fee inclusive of tutorial handout, lunch, tea- breaks
and 3% GST)
ORGANIZING COMMITTEE
Conference Chairman : Tong Yit Chow
Conference Co-Chairman : Do Manh Anh
Advisor: Tan Hong Siang
Secretary : K.T. Lau
Technical Programme : Samir Rofail
Publications & Publicity : Ng Lian Soon
Finance : Wong-Ho Duan Juat
Logistics : Ooi Tian Hock
SUBMISSION OF PAPERS
Authors are invited to submit three copies of an extended
summary of not more than 1000 words and preferably with
diagrams, illustrations and references by 28 February 1997.
Please send summary to:
The ISIC-97 Secretariat
Center for Continuing Education
Nanyang Technological University
Nanyang Avenue
Singapore 639798
Republic of Singapore
E-mail: isic97@ntuvax.ntu.ac.sg
Fax: (65) 793-0997 Tel: (65) 799 4723
KEYDATES
Submission of extended summary : 28 February 1997
Notification of Acceptance : 15 April 1997
Submission of camera-ready papers: 15 June 1997
Preliminary Registration
[_] I intend to present a paper. The abstract is attached.
Topic : ______________________________________________
[_] I intend to attend the conference. Please send me further
details and the registration form.
Surname _________________________________
First Names______________________________(Prof/Dr/Mr/Mrs/Ms)
Designation_________________Organization______________________
Address_______________________________________________________
_______________________________________________________
Country ______________________________________________________
Telephone ____________________________Fax __________________
E-Mail____________________________________
Return to Index
Return to Conference Listing
SURFACE MOUNT INTERNATIONAL (SMI)
San Jose, CA
Sept. 7-11, 1997
---------------------------------------------------
Authors are invited to submit a paper to the electronic industry's
premier forum on surface mount and related technologies for electronic
manufacturing. Abstracts should offer non-commercial, user-oriented
solutions in any of the disciplines in electronic manufacturing. Papers
will be accepted based on the submitted abstract and the judgement of the
technical program committee. Previously presented papers (published
prior to the SMI conference date), papers not complying with the
publication guidelines, and papers that describe or promote company's
products will NOT be accepted. Since the SMI paper selection process is
competitive, clearly describe your work, explain its significance and
what is new, highlight novel features, provide supporting data, include
practical results/conclusions, and references to prior work. A copy of
the manuscript, including a computer disk, must be received no later than
July 1, 1997.
Papers must comply with publication guidelines, be approximately six
pages in length, and not exceed 15 pages. Oral presentations are limited
to 20 minutes plus 10 minutes for attendee questions, and require a paper
to be published in the proceedings.
KEY TOPICS OF INTEREST
A. High density packaging
Ball grid array (BGA)
Chip scale packaging (CSP)
Flip chip/direct-chip-attach (DCA)
Substrates
Flex circuitry
B. SMT Manufacturing
Advanced SMT manufacturing
Main stream SMT manufacturing
Developments in assembly equipment
Soldering processes
Cleaning alternatives
Manufacturing defect analysis
Process control (SPC)
Design for manufacture
C. Meterials
Lead-free solders
Conductive adhesives
Encapsulants
IC packaging materials
D. Contract Manufacturing
Selection criteria
Implementing new technologies
Cost effective CMS
Contract IC packaging
E. Reliability
Solder joints
IC package
Harsh environments
FOR INFORMATION, CONTACT
Martin Barton, Conference Director
1416 Glastonberry Dr.
Plano, TX 75075-2737
Tel: +1 972-424-8805
Fax: +1 972-881-8354
Email: 75521.1574@compuserve.com
SHORT Courses
NEXT GENERATION OF ELECTRONIC PACKAGING: BEYOND MCM, FLIP-CHIP, AND BGA
Packaging Research Center
Georgia Institute of Technology
Atlanta, GA
February 10-14, 199
---------------------------------------------------
Submitted by: Debra Kelley
---------------------------------------------------
LECTURERS
This course will be taught by world class researchers and industry
experts that include Professor James Meindl, Professor Rao Tummala, Bob
Pfahl of Motorola, and 10 other professors who are doing leading-edge
research in these areas.
BACKGROUND
Low cost packaging of electronics will be one of the critical
technologies for microelectronics-based systems during the coming
decade. The next generation of packaging needs to be 10 times cheaper,
10-100 times smaller, and about 10 times faster than current packages
based on BGA, CSP, and flip-chip technologies. The Georgia Tech
Packaging Research Center expects to achieve these goals by major
paradigm shifts in a number of critical technologies that include
low-cost integrated substrate (with capacitors, resistors, inductors, and
optoelectronics) design, test, assembly, and thermal management by air
cooling.
COURSE OUTLINE
Introduction
Next Generation System Needs
Next Generation Semiconductor Technology
Next Generation of Packaging Technology
PRC Facility Tours
Next Generation Low-Cost Integrated Substrate
Low-Cost MCM
Large Area Intelligent Manufacturing
Integrated Passives - capacitors, resistors, inductors
Next Generation of Flip-Chip Assembly, Reliability, and Thermal
Management
Thermo-mechanical Reliability
Flip-chip Assembly and Underfill
Thermal Mangement by Air Cooling Beyond 1 W/cm2
Next Generation Design, Electrical Test, and System Modeling
EM, RFI, and Interconnection Models
Substrate and Assembled Module Testing
System-level Modeling
Next Generation of Optical and Wireless Packaging
WHO SHOULD ATTEND ?
This course is intended for engineers, technical managers, and research
directors involved in the development of materials, tools, and
manufacturing processes associated with electronic packaging.
Additionally, the course will provide insight into the expected
capabilities of next generation packaging for designers of systems that
have a critical dependence on state-of-the-art packaging.
COURSE SCHEDULE AND LOCATION
This course will be held at the Manufacturing Research Center on the
Georgia Tech campus in Atlanta, GA. The course will begin at 9:00 am on
Monday, February 10, 1997 and will conclude at 1:00 pm on Friday,
February 14, 1997.
FOR MORE INFORMATION
For copies of the course brochure or registration information, contact
Distance Learning, Continuing Education, and Outreach at Georgia Tech
(phone: 404-894-2400, fax: 404-894-8925). Refer to course EE-187. Other
information is available from the
Packaging Research Center (phone:
404-894-9097).
Debra Kelley
Packaging Research Center
Atlanta, GA 30332-0560
Phone:(404) 894-9097 FAX: (404) 894-0957
debra.kelley@ee.gatech.edu
Return to Index
Dec. 9-12, 1996: 2nd Int'l Symp. on Electronic Packaging Technology
Shanghai, China. fhliu@fudan.ihep.ac.cn or sliu@eng.wayne.edu.
Jan. 27-29, 1997: Recent Progress in Printed Circuit Board Technology
Berlin Germany. Dr. Elke Azkel (+49 30 464 03162).
Jan. 28-30, 1997: Semiconductor Thermal Measurement and Management Symp.
( SEMITHERM XIII)Austin, TX, USA. Info: Univ. Arizona,
Engineering Professional Development (+1 520-621-3054)
Feb. 3-5, 1997: IEEE Multi-Chip Module Conference
Santa Cruz, CA USA. Linda Pascal (+1 408 459 2263).
March 10-12, 1997: 3rd Int'l Symp. on Advance Packaging Materials: Processes
Properties, and Interfaces
Chateau Elan, Braselton, GA USA. ISHM (+1 703-758-1060).
Apr 16-18, 1997: 1997 IEMT/IMC Joint Symposium
Omiya Sonic City, JAPAN. IEMT/IMC Symp. Sec. (+81 3 5802 5366).
June 15-19, 1997: INTERpack '97. The Pacific Rim/ASME Int'l Intersociety
Electronic and Photonics Packaing Conf.
Hawaii USA. Dr. Ephraim Suhir (+1 908 582 5301).
Sept. 7-11, 1997: Surface Mount International (SMI).
San Jose, CA, USA. Info: Martin Barton (+1 972-424-8805).
Return to Index
To submit web sites (including yours) for
addition to the list, feel free to email them to pkg_news@msrc.wvu.edu.
In this case, you can provide a summary of the activities of the
company/group represented by the web site.
- SynRad
CO2 laser marking systems for ic packages and pcb's. Includes full catalog
pages and descriptions of a range of CO2 lasers and laser marking systems for
electronic components.
- TIMA (France)
Wide range of VLSI design, CAD, MCM, MEMS, etc. in this major European site.
- E.E.E.
Friedman (Delft) Research on optical interconnections, neural processing.
- Advanced CAM Technologies, Inc.
Computer-Aided Manufacturing software for PCBs.
- Aercology Corp.
Worksite air management systems.
- AIM Products, Inc.
No-clean solder materials.
- Amistar Corp.
PCB production equipment.
- Artwork Conversion Software, Inc.
Software for translation of files (e.g., DFX to Gerber).
- Automated Design, Inc.
Software tools for PCB design analysis.
- AVX Corp.
Components, including low inductance bypass capacitors.
- BB Custom Circuit Supplies.
New and refurbished equipment sales.
- Cadsoft Computer, Inc.
PCB design software (including "EAGLE").
- Coates ASI.
PCB chemicals (soldermask, etc.).
- Cooper and Chyan Technology, Inc.
PCB CAD software (including "SECTRA" autorouter).
- DDE Corp.
PCB layout software tools, including high speed, RF, etc.
- Dispensing Technologies Int'l Corp.
Dispensing systems.
- Electronic Controls Design, Inc.
Control systems for PCB manufacture (e.g., "WaveRIDER").
- Electronics Packaging and Production
Magazine home page.
- Everett Charles Technologies.
Board test systems.
- Hyperlynx, Inc.
PCB design/simulation software.
- Instrument Specialties
Corp. Metal materials, EMI/RFI shielding materials.
- Intercept Technologies, Inc.
Cad-to-CAM software.
- IPC home page.
Professional society.
- IRC Corp.
Passive networks (R, R-C, etc) on silicon substrates.
- ISHM (the Microelectronics Society)
site. Professional society.
- LEISTER ELectro-Geratebau.
Contactless soldering and de-soldering equipment.
- LPKF Cad/CAM Systems, Inc.
Circuit board prototyping systems ("PROTOMAT").
- Metcal Corp.
PCB rework and repair systems.
- Microsim Corp.
Cad tools for electronics ("PSPICE", pcb design, etc).
- Miller Freeman Corp.
Fabrication news (publisher of "Printed Circuit Fabrication).
- Nanomics Corp.
Connectors, terminations, etc. for PCBs.
- OK Industires Inc.
Systems/tools for PCB assembly.
- Orcad, Inc.
PCB design/layout software tools.
- Pace, Inc.
PCB assembly, rework and repair systems.
- PADS Software.
PCB design software tools.
- Perfection Products, Inc.
MCM-hybrid substrate handling equipment.
- Philips, Corp.
Metal packaging, process equipment.
- Protel Technology Corp.
PCB design, simulation CAD tools.
- Rogers: Microwave and Circuit Materials
Div.
Circuit board materials.
- Router Solutions, Inc.
Interface software tools for CAE/CAD/CAM of PCBs.
- Samtec Corp.
Interconnections/connectors.
- SMT Plus Inc.
Books on packaging technologies.
- Surface Mount Tech Association.
Professional society.
- Teradyne, Inc.
High density connectors, etc. for PCBs.
- T-Tech, Inc.
Circuit board prototyping system.
- Unidyne International Inc.
New and used equipment sales.
- Veribest, Inc.
PCB design software (including "PCB Signal Analyzer").
- Wise Software Solutions, Inc.
PCB software (including "GerbTool").
- Yamaichi Electronics USA, Inc.
KGD and chip-scale packaging, burn-in sockets, emulators, etc.
- Zuken-Redac.
PCB design software tools (including "CADSTAR", "VISULA").
Return to Index
Editor: Charles A. Harper.
Topics (description from advertisement)
Packaging materials: How to select the right plastics, ceramics and
metals.
Thermal management: How to minimize heat in increasingly dense
electronic assemblies.
Rigid and flexible printed wiring boards: Design, manufacture, and
application of all types of PWBs.
Packaging and interconnecting ICs and semiconductor devices: Complete
guidelines including electrical, mechanical, thermal, and material
parameters.
State of the art packaging methods for microwave systems, high-speed
digital systems, hybrid microelectronics, electro-optical systems,
high-voltage systems, and more.
INFO: 1067 pages, 600 illustrations. Order #026684-0. Price: $84.50.
PUBLISHER: McGraw-Hill,PO Box 182606,Columbus, OH 43272-3033
Tel: 1-800-2 MCGRAW; Fax: 1-614-759-3644
Electronic Packaging Techniques that Save Time and
Money contains 1067 pages, with 600
illustrations. Order #026684-0. Price: $84.50.
Publisher: McGraw-Hill,PO Box 182606,Columbus, OH 43272-3033
Tel: 1-800-2 MCGRAW; Fax: 1-614-759-3644
Author: Jennie S. Hwang.
Description (from advertisement)
Apply the basics of soldering to the sophisticated application of surface
mount, fine pitch, solder joints, and other electronic assembly and
manufacturing issues that are changing the electronics industry. Thoroughly
covering one of the highest profile subjects in electronics packaging and
interconnection, this volume is a thorough and practical guide to
state-of-the-art.
You'll learn about application of solders to cutting edge bump grid array
issues, importance and impact of solder joint quality and reliability, new
and emerging specifications and standards, types and applications of various
solder compounds, etc.
Modern Solder Technology for Competitive Electronics Manufacturing
contains 640 pages. Order #031749-6. Price: $75.00.
Publisher: McGraw-Hill,PO Box 182606,Columbus, OH 43272-3033
Tel: 1-800-2 MCGRAW; Fax: 1-614-759-3644
Editor: John Lau.
Description (from advertisement)
Here's everything you need to put state-of-the-art BGA technology to
work in packaging and interconnecting today's high performance, high density
electronic devices.
You'll see how to use ceramic and plastic substrates; route printed
circuit boards; package ceramic ball, column grid, and plastic ball arrays;
assemble CBGAs and PBGAs; magage CBGA and PBGA thermal and electrical
performance; assure the reliability of BGA solder joints, and
more.
Making Ball Grid Array Technology contains 656 pages, with 260
illustrations. Order #036608-X. Price: $75.00.
Publisher: McGraw-Hill,PO Box 182606,Columbus, OH 43272-3033
Tel: 1-800-2 MCGRAW; Fax: 1-614-759-3644
Editor: John Lau.
Description (from advertisement)
state-of-the-art guidance on how to select the most cost
effective flip chip design and manufacturing process for today's generation
of high-density, high performance electronics devices.
Topics include IC chip yield; KGD definition, testing and cost; MCM
yield; solder bumped flip chip technologies; wired flip chip technologies;
anisotropic conductive flip chip technologies; TAB flip chip technology
(CSP); metallurgy bumped flip chip technologies; etc.
Flip Chip Technologies contains 565 pages, with 445
illustrations. Order #036609-8. Price: $79.00.
Publisher: McGraw-Hill,PO Box 182606,Columbus, OH 43272-3033
Tel: 1-800-2 MCGRAW; Fax: 1-614-759-3644
Author: Vern Solberg.
Description (from advertisement)
Still the only book to focus on design for manufcturing of surface mount
PC boards, the new edition features the latest breakthroughs in fine pitch
and ball-grid array devices. You'll get step-by-step guidance from one of
the industry's best-known experts for developing the most cost-effective
products possible using SMT.
Design Guidelines for Surface Mount and Fine Pitch Technology, 2nd
edition contains 288 pages, 100 illustrations. Price:
$52.00.
Publisher: McGraw-Hill,PO Box 182606,Columbus, OH 43272-3033
Tel: 1-800-2 MCGRAW; Fax: 1-614-759-3644
Author: Clyde Coombs, Jr.
Description (from advertisement)
Now completely revised to include advances n PCB fabrication and assembly
technology, the Fourth Edition provides the same type of practical
problem-solving information on component packaging and board and assembly
engineering and design that has made it a standard for printed board
fabrication.
Topics covered are:
- Designing and engineering for performance and manufacturability
- Developing an effective computer-aided design process
- Selecting computer tools for PCB design and simulation
- Understanding and using SMT and MCM technologies
- and much more.
Printed Circuits Handbook, 4nd edition contains 900 pages, 800
illustrations. Price:
$89.50.
Publisher: McGraw-Hill,PO Box 182606,Columbus, OH 43272-3033
Tel: 1-800-2 MCGRAW; Fax: 1-614-759-3644
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Submitted by Paul Wesling:
Table of
Contents for upcoming/current issues of the IEEE Trans. on Advanced
Packaging. Each quarter, this location will be updated with the next Table of
Contents.
For information on subscribing to this quarterly journal (800 pages/year;
about 100 papers), call IEEE (in the USA tollfree at 1-800-678-IEEE) and
ask for publication 021-1651. Subscriptions are $250/year (non-IEEE
members). You may wish to join IEEE (members get substantial discounts);
if so, request information from IEEE or contact p.wesling@ieee.org for
information.
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